Abhishek Chatterjee

Software Engineer

Bengaluru, Karnataka, India12 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

8 years of experience in Design Verification.
Expertise in System Verilog and UVM.
Proven track record in developing complex verification IPs.

Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in functional verification and protocol development.

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Skills

Core Skills

Functional VerificationUniversal Verification Methodology (uvm)

Other Skills

MIPI RFFE VIPTestSuite DevelopmentFunctional ChecksCoverageDebug portsVerification IP developmentUFS TestSuiteBUS protocolMIPI MPHYVerilog HDLDigital Logic DesignDigital CMOS VLSI DesignCC++Data Structures

About

8 years of experience in Design Verification domain with strong background in System Verilog, UVM, VIP , TB & TestSuite Development for Serial communication & BUS Protocols.

Experience

12 yrs 8 mos

Total Experience

3 yrs 2 mos

Average Tenure

5 yrs 1 mo

Current Experience

Nvidia

Senior Engineer

Mar 2021 – Present · 5 yrs 1 mo · Bengaluru, Karnataka, India

Qualcomm

2 roles

Senior Lead Engineer

Dec 2019 – Mar 2021 · 1 yr 3 mos · Bengaluru, Karnataka, India

Senior Engineer

Nov 2017 – Dec 2019 · 2 yrs 1 mo · Bengaluru, Karnataka, India

Part of Multimedia & Graphics group.
Working on Low Power Audio System & Digital Signal/Image Processing block.

Synopsys inc

2 roles

Senior R & D Engineer

Promoted

Dec 2015 – Nov 2017 · 1 yr 11 mos · Bengaluru, Karnataka, India

Developed MIPI RFFE VIP & TestSuite.
As part of that activity been involved in developing several key protocol features in VIP.
Worked on various Verification features such as Functional Checks, Coverage, Exceptions, Callbacks, Passive Component, Debug ports, Trace files.
Developed several TB components such as Scoreboards, System monitors, Tests to meet coverage goals.
Had a chance to work with several key accounts.
Helped them to get through their initial TB bring up & to achieve their coverage goal.
Been part of MIPI SLIMbus & MIPI SPMI VIP Development.

MIPI RFFE VIPTestSuite DevelopmentFunctional ChecksCoverageDebug portsFunctional Verification+1

R&D Engineer-II

Jun 2013 – Oct 2015 · 2 yrs 4 mos · Bengaluru, Karnataka, India

Worked as Verification IP developer for MIPI UniPro Revision 1.41, 1.61 & 1.8.
Got an opportunity to develop UFS TestSuite (Memory Controller as well as Memory Device) from Scratch to verify SNPS IIP as well as VIP.
Had hands on experience on BUS protocol e.g. AXI/APB/AHB.
Been involved in developing UniPro TestSuite, writing CTS testcases.
Had a good exposure of MIPI MPHY which had been part of UniPro/UFS Stack.

Verification IP developmentUFS TestSuiteBUS protocolMIPI MPHYFunctional VerificationUniversal Verification Methodology (UVM)