Sudeep Saha

Engineering Manager

Bengaluru, Karnataka, India20 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Led teams delivering industry-first IPs
Expert in high-speed analog layout design
Strong risk management and stakeholder communication

Stackforce AI infers this person is a leader in semiconductor design with a focus on analog layouts and high-speed IP development.

Contact

Skills

Core Skills

Analog LayoutsIp DevelopmentCustom LayoutsExecution PlanningLayout IntegrationCustom LayoutAms Training

Other Skills

Team ManagementRisk MitigationUSBPHYHDMI PHYLayout GuidelinesVirtuoso Layout XLCalibreAssuraDRCLVSFloorplanningCadence VirtuosoVLSISoCCMOS

About

Dynamic & result oriented technical leader with strong leadership experience in delivering full custom analog layouts for various high-speed IPs like DDR, UCIe, DisplayPort, HDMI, USB PHY etc. across process nodes; currently working as Senior Engineering Manager for Analog Layouts at Intel India. Key skills & strengths - • Manage and develop high performance teams, delivering many industry-first IPs • Strong risk-identification and mitigation skills • Inter-disciplinary collaboration with cross functional teams across multiple timezones • Strong inter personal & communication skills with effective stakeholder management • Reinforce and role model cultural values and behaviours • Vast hands-on experience of building critical analog layouts for various high speed IPs • Experience in full custom analog IP top layout integration including flip-chip/wire-bond integration • Closure of ESD and Reliability checks for custom layout design

Experience

20 yrs 6 mos

Total Experience

6 yrs 10 mos

Average Tenure

11 yrs 10 mos

Current Experience

Intel corporation

2 roles

Engineering Manager

Promoted

Oct 2020 – Present · 5 yrs 6 mos

• Leading the analog layout team owning and delivering various IPs for Intel's mainstream SOCs (DDRPHY, UCIe, HBM etc.)

Analog LayoutsIP DevelopmentTeam Management

Sr. Analog Layout Design Engineer

Jun 2014 – Present · 11 yrs 10 mos

Lead Analog Layout Engineer, driving execution of complete custom layouts for high speed DISPLAY PHY across process nodes for various SOCs
Developed efficient execution plan, laying guidelines, proactively tracking status, identifying & mitigating risks, thereby ensuring on-time high quality analog layout deliverables for the IPs.
Owned and delivered layout of critical sensitive analog blocks in latest process nodes' ensuring quality & reliability coverage

Custom LayoutsExecution PlanningRisk Mitigation

Freescale semiconductor

Sr. Analog Layout Design Engineer

Feb 2007 – May 2014 · 7 yrs 3 mos

Lead analog layout activities for USBPHY & HDMI PHY design's in various technologies
(90nm, 65nm, 45soi, 28nm, Internal technology)
Owned entire IP top layout integration including flip-chip & wire-bond connectivity
Owned & delivered complete HDMI PHY top layout using custom layout tool, including layout draw of each individual block in entire hierarchy within very strict timelines
Delivered high quality custom layout’s of various critical analog design blocks like high-speed transmitter, receiver, precision ADCs etc.

USBPHYHDMI PHYLayout IntegrationCustom Layouts

Wipro technologies

Analog Layout Design Engineer

Aug 2005 – Jan 2007 · 1 yr 5 mos

Worked at client site for Intel,Bangalore
Worked on Wipro's internal development projects for custom layout of LNA & other analog circuits
Being one of the first few member of the newly formed AMS team, developed layout guidelines, AMS training documents for new joiners

Custom LayoutAMS TrainingLayout Guidelines