Kuldeep Sharma

Software Engineer

Delhi, India14 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in VLSI design and verification methodologies.
Proficient in System Verilog and UVM environments.
Strong background in developing verification IP for industry standards.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in verification methodologies and system design.

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Skills

Core Skills

Verification MethodologiesSystem Verilog

Other Skills

UVMAXI VIPCData Integrity CheckersTop Level TestbenchCPRI VIPRAL testcasesTestplan CreationTX ImplementationVerification IP DevelopmentSVAFunctional CoverageDigital ElectronicsVerilog-AUnix

About

OBJECTIVE: Intend to work as a key player in leading corporate of high tech environment in field of VLSI design and verification, where I can explore myself and utilize my potential. SKILL SET: - Language: C, C++, HDL, VHDL, Verilog, System-Verilog - Verification Methodologies: UVM - Bus Protocols: AMBA : AXI4, AXI3, AHB3.0, APB, AXI4_STREAM - Serial Protocols: I2C, MHL - Simulation Tools Used: Model Sim, VCS, NC Verilog - Debugging Tools Used: Verdi, DVE, Simvision - Platforms: MS-DOS, Windows 98/XP/VISTA/7, Linux - Repositories: Perforce - Computer Exposure: MS Word, MS Power Point, MS Excel AREAS OF EXPERTISE: -Good experience in development of complete System Verilog environment (Generator/Driver/Monitor/Scoreboard). - Creation of passive verification components (bus monitor) from scratch in UVM. - Creation of verification environment, high-level modelling based on Verilog. - Expertise : TestPlan, Coverage Plan, Assertion Plan. - Code maintenance of Verification Suite, implementation of new enhancements and bug fixing. - Coding and execution of Test Cases in Verilog and System Verilog (UVM). - Timely support to the customers. - Integration and creation of new environments. - Release packaging, validation, documentation (User Guide/ Release notes) updates and regression. - Supporting client interaction for the evaluation and execution of the product and bug fixing. - Clear understanding of domain, language and tools used in the protocol.

Experience

14 yrs 7 mos

Total Experience

2 yrs 1 mo

Average Tenure

4 yrs 8 mos

Current Experience

Intel corporation

Senior Design Engineer

Aug 2021 – Present · 4 yrs 8 mos · Bengaluru, Karnataka, India

Altran

2 roles

Technical Lead

Jul 2020 – Aug 2021 · 1 yr 1 mo · Noida, Uttar Pradesh, India

Working with Intel on Sub-system/IP Verification
Worked on a CRSS -Sub-System Verification.
Implemented UVM environment to preload the data in the memory from
SV testbench
Understanding the complete subsystem flow and write data integrity
checkers at each interface (around each blocks) in the subsystem.
Integrated AXI VIP in the subsystem in UVM environment
Complete Code coverage with target.
Wrote C testcases.
Verified Reader/Writer Block for Subsystem.
Write sequences & testcases for Reader/ Writer verification
Verified Clock gate feature, threshold feature of Sub-system with the
help of assertion.

UVMAXI VIPCData Integrity CheckersVerification MethodologiesSystem Verilog

Senior Engineer

May 2018 – Jun 2020 · 2 yrs 1 mo · Noida, Uttar Pradesh, India

Worked as a FPGA Verification Engineer on latest technology Makalu Split , Makalu 5G.
Understanding the specification and verified the Sub-system as per the design specification.
Implemented complete Top Level Testbench for all Minihub subsystem.
Integrated CPRI VIP in Makalu-5G as a Master & Trif Scoreboard for Downlink path to compare IQ Data.
Worked on RAL testcases for register verification.

Top Level TestbenchCPRI VIPRAL testcasesVerification MethodologiesSystem Verilog

Ust global

Technical Analyst

Jun 2017 – Mar 2018 · 9 mos · Noida Area, India

Worked as a IP verification .

Synopsys inc

Design and Verification Engineer

Mar 2015 – Jun 2017 · 2 yrs 3 mos · Delhi Area, India

Working with Quallcom in QSB-AHB,QSB-AXI ,Nvs-AHB.
Roles & responsibility:
1) Development for new enhancement.
2) Created testcases for verification point -of view.
3) Working on coverage.
4) Debugging customer issue .

Einfochips

Design Verification Engineer

Sep 2014 – Mar 2015 · 6 mos · Ahmedabad Area, India

Worked on MHL (Mobile High Definition Link) .
Role and responsibility :
1) Created Testplan for TMDS interface or CBUS interface.
2) Implementaion of TX of CBUS interface.

Testplan CreationTX ImplementationVerification Methodologies

Truechip solutions

IC2 Design Engineer

Oct 2011 – Aug 2014 · 2 yrs 10 mos · Noida

Development of Verification IP for industry standard protocols used in an ASIC/FPGA or SOC. AXI4, AXI3, AHB3.0 ,APB, I2C, AXI4_STREAM. Write SVA (System Verilog Assertion ) , Functional Coverage , Sequences, Testcases.

Verification IP DevelopmentSVAFunctional CoverageVerification Methodologies

Cdac,noida

Post Graduate Diploma

Feb 2011 – Jul 2011 · 5 mos · Noida Area, India

I have completed 6 months post graduate diploma in VLSI. Learn Verilog , VHDL, C, C++. I have completed project of AES ( Advanced Encryption Standard) in verilog language.
Advanced Encryption Standard is an approved cryptographic algorithm that can be used to protect electronic data. The AES algorithm is a block cipher that can encrypt and decrypt digital information.