R

Rajyalakshmi Gurugubelli

Software Engineer

Eluru, Andhra Pradesh, India1 yr 2 mos experience

Key Highlights

  • Expertise in Physical Design and VLSI.
  • Proficient in Static Timing Analysis and DFT.
  • Hands-on experience with Synopsys tools.
Stackforce AI infers this person is a VLSI Design Engineer with a focus on Physical Design and ASIC development.

Contact

LinkedIn

Skills

Core Skills

Physical DesignVery-large-scale Integration (vlsi)

Other Skills

SynthesisPNRDesignApplication-Specific Integrated Circuits (ASIC)Layout Versus Schematic (LVS)Design ToolsDFTPower IntegritySignal IntegrityTiming ClosureRTL DesignTimingDesign Rule Checking (DRC)IR dropSynopsys tools

Experience

1 yr 2 mos
Total Experience
1 yr 2 mos
Average Tenure
1 yr 2 mos
Current Experience

Mediatek

Physical Design Engineer

Mar 2025 – Present · 1 yr 2 mos · Banglore · On-site

SynthesisPNRDesignApplication-Specific Integrated Circuits (ASIC)Very-Large-Scale Integration (VLSI)Layout Versus Schematic (LVS)+22

Rv skills design centre

ASIC Physical Design Engineer Trainee

Jul 2024 – Feb 2025 · 7 mos · Banglore · On-site

Physical DesignStatic Timing Analysis

Education

Sri Vasavi Engineering College

Bachelor of Technology - BTech

Jan 2020 – Jan 2024

NRI Junior College Eluru

Intermediate — MPC

Jun 2018 – Present

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