Jul 2003 – Mar 2006 · 2 yrs 8 mos

• Worked on several projects in the physical design:
• + 130nm ASIC Burbank (first 130nm design for GNSS)(DTV/LCD monitor chip)
• + Physical design of 180nm ASIC (Insam) (multi function monitor display chip)
• + IR/EM analysis of the various 180nm asic like Hudson, Tuscon, frontier and phoenixU monitor SOC.
• Responsiblity
• + Productization of the chip involving the methodology development and flow development for the physical design.
• + Developed make-flow using the synopsys tools PC and Astro to perform the physical synthesis and routing.
• + Worked on the floorplan, power grid design,CTS,routing, extraction,DFM implementation,IR/EM analysis.
• + IO ring design to meet the Power delivery/ESD requirement and IR/EM requirement of the chip.
• + Integration of analog macros while understanding requirements of the gaurd-rings, substrate noise, ESD, etc
• + Physical verification Antenna/LVS/DRC/DFM using teh Calibre.
• + Development of utility runsets in calibre for example to find floating gates in design.
• + Implementation of the ECOS, development of the metal eco methodology, decap estimation/addition and design of decap cells.
• + Library collaterals verification and Library preparation of the macros.

Aug 2001 – Jul 2003 · 1 yr 11 mos

• LVDS Receiver in 0.13um technology10 Bit, 108Mhz High speed LVDS Receiver
• Responsibilities: Architecture, Design, simulation, and integration of LVDS receiver. The individual blocks involved are Analog front end – input buffer /equalizer amplifier, sampler and Phase locked loop for high speed clock (800Mhz) generation and right sampling phase recovery and serial to parallel converter. The challenge involved is to generate right sampling phase for perfect data recovery, eye - equalization of received data and sampling of data.
• Mini-LVDS, LVDS & RSDS Transmitter integrated in
• TSMC 0.18um LogicTechnology :To drive the column drivers on the Flat Panel Monitors: Design, simulation, integration, layout and physical design, LVS and DRC check of Mini-LVDS and RSDS and integration of LVDS, Mini-LVDS and RSDS in a single integrated solution to achieve better performance and reduction in area. The challenge was involved in generation of the high-speed clocks for a wide range of frequencies accurately for serialization on the dual edge of the clock. The another challenge was to have integrated driver for the Mini-LVDS, RSDS and LVDS which can do high speed (250Mhz to 1.65Ghz) drive up to 10m of cable length accurately with varying eye opening requirements for the macro (150mv to 900mv).
• DVI Transmitter for 0.18um Technology:It consists of a 10:1 parallel to serial converter, a PLL which gives clock to the Serializer, Output driver and Band-gap reference circuit. The challenge involved in was to serialize input data (25 MHz to 165 MHz) to 10 times speed (250 MHz to 1.65 GHz).
• Responsibilities: Involved in design of architecture, design and integration of circuits, simulation of circuits, and layout using Cadence Virtuoso, LVS and DRC using Calibre and Hercules.
• Band-gap reference circuit for 3.3v, 0.18um Responsibilities:Schematic Capture was done using Virtuoso schematic composer and layout was done in Virtuoso layout editor, simulations was done using hspice.

Aug 2000 – Aug 2001 · 1 yr

• Digital Capture PLL:Clock Recovery circuit for data capture on front end.The main challenge was to transfer the design from 0.25um design into 0.18um technology.
• Responsibilities: Modeling of the individual blocks of PLL in Verilog.
• Flamingo (FLI2300):A de-interlacer, scaler, and enhancer (Digital Format Converter) chip for TV and DVD segment.
• Responsibilities:
• + Handled the verification of vertical scalar, Frame Rate Converter (FRC) and the SDRAM Controller. The SDRAM controller has 2 write clients and 8 read clients and has bandwidth of 160 MHz.
• + Developed the pseudo clients (de-interlacer and Vertical Scalar) in Verilog for the SDRAM controller to verify it. Designed the Interface for the memory (64x40 RAM and 64x32 RAM) with the vertical scaler, horizontal scaler and The external host (ex. Micro-controller or I2C).
• + The integration of the memory controller into the full chip and verified it.
• + Designed the double buffering module for the critical registers in the chip, which normally involves in the mode change of the chip by the users.
• Integrated the double buffering module and verified in the full chip.
• + Designed the frame rate conversion bypass mode that involves choice of FIFO and interface of FIFO with Vertical Scalar and integrated it.
• + Full chip netlist simulation of flamingo by NC-Verilog and Verilog-XL.
• Jag2S: Display Processor with a Timing Controller targeted for LCD monitors.
• + Verification of scaler and Design of the transition minimization block to be used for minimizing the transitions on a 48 /24/18 bit wide bus to be interfaced with the LCD panel.
• Responsibilities:
• Synthesis and physical design of the Micro-controller core to target Xilinx Vertex Series FPGA for verification of the core.