Ayushi Gupta — Software Engineer

I am a Staff Engineer specializing in ASIC synthesis, static timing analysis, and ultra‑low‑power optimization for complex SoCs at advanced technology nodes. Over 6+ years at MediaTek Bangalore, work done by me:• led block‑level MCMM physical synthesis for high‑volume display macros and SoC designs with 3M–5M instance counts and 1 GHz clocks, consistently meeting aggressive PPA targets.• Delivered first‑pass silicon success with <2% timing margin violations while cutting leakage power by 12–18% and total power by up to 15–20% compared with baselines. • Expert in SDC constraint development, STA across all corners/modes, and ECO generation, with 50+ ECOs implemented to systematically resolve setup/hold violations and achieve <100 ps slack margins within spec.Hands‑on with Genus, Fusion Compiler, Innovus, PrimeTime, Conformal LEC, CLP, and TimeVision. SDC across full digital implementation flows from RTL to pre‑STA integration. Known as an ASIC synthesis and timing closure SME, with a 99.2% first‑pass quality rate and consistent delivery of production‑ready synthesis databases enabling 100% timing closure at backend.Trusted technical leader who mentors RTL design teams on synthesis‑friendly coding, partners closely with Physical Design and Manufacturing on floorplan, scan DRC, and test optimization, and drives cross‑functional workflows that reduce design cycle time by ~15%. Passionate about cutting‑edge process nodes, low‑power design, and building robust, scalable methodologies for next‑generation semiconductor products.

Stackforce AI infers this person is a Semiconductor Design Engineer specializing in ASIC synthesis and low-power optimization.

Location: Bengaluru, Karnataka, India

Experience: 7 yrs 3 mos