Romal Pratap

Director of Engineering

Bengaluru, Karnataka, India25 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

25+ years in semiconductor design leadership.
Proven first-pass silicon success across multiple technology nodes.
Expertise in automotive safety and mixed-signal IC design.

Stackforce AI infers this person is a Semiconductor Engineering expert with a focus on automotive safety and mixed-signal IC design.

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Skills

Core Skills

Analog & Mixed-signal Ic DesignPmicHigh-speed PhyAutomotive Asic DesignFunctional Safety

Other Skills

Voltage RegulatorsUCIE 2.0GDDR7SerDesData Converters (ADC/DAC)Power Delivery ArchitectureAdvanced Node Design (3nm, 5nm)Silicon ValidationAEC-Q100ISO 26262Sigma-Delta ADCAutomotive SPICEFailure Mode AnalysisEMC/PSRRHigh-Speed PHY (UCIE, GDDR7)

About

Accomplished semiconductor design leader with 25+ years of expertise in analog and mixed-signal IC design, custom ASIC development, and power management ICs (PMICs). Currently leading advanced power delivery solutions, high-speed PHY interfaces (UCIE, GDDR7, SerDes), and data converter IP design for Intel’s next-generation processor and memory platforms. Proven track record in silicon product delivery with first-pass success across multiple technology nodes (Intel 3nm, 7nm; TSMC 5nm, 65nm). Experienced in voltage regulators, DC-DC converters, LDO design, sigma-delta ADC, SAR ADC, PLL design, and die-to-die interconnect solutions. Strong background in Functional Safety (ISO 26262), AEC-Q100 qualification, DFSS, and Automotive SPICE for safety-critical ASICs. Skilled in technology roadmap planning, team leadership, and cross-functional collaboration, enabling high-performance mixed-signal IP development. Core expertise: Analog Circuit Design | Mixed-Signal IC Design | PMIC Architecture | High-Speed PHY Design | Data Converter IP | Automotive Safety & Quality | Advanced Node Design (3nm to 90nm)

Experience

25 yrs 6 mos

Total Experience

6 yrs 4 mos

Average Tenure

8 yrs 10 mos

Current Experience

Intel corporation

2 roles

Director of Engineering

Promoted

Apr 2024 – Present · 2 yrs

Engineering Manager

Jun 2017 – Mar 2025 · 7 yrs 9 mos

Lead analog and mixed-signal design for power management ICs, voltage regulators, data converters, and high-speed I/O (UCIE, GDDR7, SerDes) across Intel’s processor and memory platforms.
Delivered PMIC architecture for Intel’s 11th Gen Core processors, reducing platform footprint , achieving first-pass silicon success .
Directed Optane Memory PMIC system, ensuring reliability and reducing system-level power .
Developed fully integrated voltage regulators with digital control, improving power efficiency
Delivered GDDR7 PHY solutions, enabling chiplet integration and multi-die packaging strategies. Hardened IPs with multiple test chips
Managed technology roadmap, team leadership (15+ engineers), and mixed-signal validation frameworks, reducing defect injection rates.
Key Skills Integrated: Analog & Mixed-Signal IC Design, PMIC, Voltage Regulators, High-Speed PHY, UCIE 2.0, GDDR7, SerDes, Data Converters (ADC/DAC), Power Delivery Architecture, Advanced Node Design (3nm, 5nm), Silicon Validation.

Analog & Mixed-Signal IC DesignPMICVoltage RegulatorsHigh-Speed PHYUCIE 2.0GDDR7+5

Robert bosch engineering and business solutions ltd.

Senior Project Manager

May 2005 – Jun 2017 · 12 yrs 1 mo · India

Delivered three generations of automotive accelerometer ASICs for airbag applications, achieving AEC-Q100 qualification, ISO 26262 compliance, and zero field failures.
Designed MEMS-based sensors, analog front ends, and sigma-delta ADC-based converters for safety-critical automotive systems.
Implemented FMEA, DRBFM, and EMC/PSRR compliance methodologies, ensuring first-pass success and robust noise immunity.
Key Skills Integrated: Automotive ASIC Design, Functional Safety, AEC-Q100, ISO 26262, Sigma-Delta ADC, Automotive SPICE, Failure Mode Analysis, EMC/PSRR.

Automotive ASIC DesignFunctional SafetyAEC-Q100ISO 26262Sigma-Delta ADCAutomotive SPICE+2