Rajesh Challa — Software Engineer
To be more Precise, i Worked & have been working as a Physical Verification(phyv) Engineer to 6nm,7nm,12nm,14nm projects (both block and chip level) and i have Hands on experience in FCRDL/IORDL generation over a chip,which includes the HDMIM,SHDMIM works. Good understanding on ESD and PERC demonstrated experience on PNR Flow and STA fixes. I have good practice on calibre and ICC tools. I can analyse things keenly and make things automate using my scripting knowledge.
Stackforce AI infers this person is a semiconductor design engineer with expertise in physical verification and static timing analysis.
Location: Hyderabad, Telangana, India
Experience: 9 yrs 4 mos
Skills
- Physical Verification
- Static Timing Analysis
Career Highlights
- Expertise in physical verification for advanced nodes.
- Hands-on experience with FCRDL/IORDL generation.
- Strong scripting skills for automation.
Work Experience
AMD
Member of Technical Staff (1 yr 9 mos)
Sr sillicon Design Engineer (3 yrs 11 mos)
Synapse Design Inc.
Senior design Engineer [HW-PD/PV] (1 yr 1 mo)
Soctronics
Physical verification and Design engineer (4 yrs 4 mos)
VEDA IIT
Vlsi Engineer Trainee (8 mos)
Education
Diploma at Government institute of electronics , hyderabad
