Sasidhar Reddy Marella

Product Engineer

Bengaluru, Karnataka, India3 yrs 6 mos experience

Highly Stable

Key Highlights

Expert in Netlist-to-GDSII implementation.
Proven track record in timing closure and optimization.
Experience with advanced node technologies.

Stackforce AI infers this person is a Semiconductor Design Engineer specializing in Physical Design and Low-power SoC implementations.

Contact

Skills

Core Skills

Physical DesignLow-power Design

Other Skills

Static Timing AnalysisPlace & RoutePhysical VerificationFusion compilerinnovuCMOSVery-Large-Scale Integration (VLSI)

About

Physical Design Engineer with 3 years' experience in Netlist-to-GDSII implementation across TSMC 3nm/4nm/7nm nodes. Skilled in timing closure, IR/EM optimization, and signoff verification using Cadence & Synopsys toolchains. Proven track record of delivering PPA-optimized, tapeout-ready SoCs under aggressive schedules.

Experience

3 yrs 6 mos

Total Experience

2 yrs 9 mos

Average Tenure

6 mos

Current Experience

Moschip®

Physical Design Engineer

Nov 2025 – Present · 6 mos · On-site

Mediatek

Project Engineer

Sep 2022 – Mar 2025 · 2 yrs 6 mos · Bengaluru, Karnataka, India · On-site

Client

Synapse design inc.

Project Engineer

Jun 2022 – Jul 2025 · 3 yrs 1 mo · Bengaluru, Karnataka, India

Experienced Physical Design Engineer with hands-on expertise in advanced node technologies including 3nm, 4nm, and 7nm. Proven track record in driving full RTL-to-GDSII implementation for high-performance, low-power SoC designs. Strong background in floorplanning, placement & routing, clock tree synthesis (CTS), timing closure, and physical verification (DRC/LVS).

Static Timing AnalysisPlace & RoutePhysical DesignLow-power Design