Sumanth Babu Lavanuru — Software Engineer
1. Having experience of Physical design flow from Netlist to GDSII for block level implementation and top level implementation. 2. Experience in PNR with Synopsys ICC2, Timing closure with Prime time, Synthesis with Design Compiler, LEC with formality, Physical Verification with IC Validator. 3. Experience in all sign-off checks (LVS, DRC, IR, LEC). 4. Experience of methodologies of Floor planning, Power planning, Place & Route, Layout verification, and resolving timing violations. 5. Having experience on integrating the IP blocks in chip level. 6. Knowledge in Static timing analysis, ECO generation. 7. Knowledge in using the text processing tools like sed, grep, regex and Text editing tools like gvim. 8. Familiar with scripting languages like Perl, Tcl.
Stackforce AI infers this person is a Physical Design Engineer specializing in semiconductor design and verification.
Location: Bengaluru, Karnataka, India
Experience: 7 yrs 9 mos
Skills
- Physical Design
- Timing Closure
Career Highlights
- Expert in Physical Design flow from Netlist to GDSII.
- Proficient in timing closure and synthesis methodologies.
- Experienced in integrating IP blocks at chip level.
Work Experience
Intel Corporation
Physical Design Engineer (1 yr 10 mos)
Adept Chips Services Pvt Ltd
Senior Physical Design Engineer (1 yr 2 mos)
Physical Design Engineer (2 yrs 7 mos)
Cerium Systems
Physical Design Engineer (2 yrs 2 mos)
Education
Bachelor of Technology - BTech at JNTU Anantapur
