Dhanwanth Varala

Software Engineer

Bengaluru, Karnataka, India8 mos experience

Key Highlights

Expert in developing UVM testbenches for complex ASIC designs.
Achieved 100% functional coverage in verification processes.
Strong leadership and communication skills demonstrated in team roles.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC design and verification methodologies.

Contact

Skills

Core Skills

SystemverilogUniversal Verification Methodology (uvm)Leadership

Other Skills

Code CoverageHardware EngineeringDebuggingCommunicationDigital ElectronicsHardware TestingAnalog SemiconductorsInternet of Things (IoT)Video AnalyticsTransformersScikit-LearnPandas (Software)Problem SolvingUnixLogic Gates

About

I am a Design Verification Engineer on the Infra Silicon team at Meta. We build custom ASICs to create a faster and more efficient infrastructure for our global systems. I enjoy the challenge of verifying complex RTL designs and ensuring our hardware is flawless. I am always eager to learn new technologies and I am driven by the goal of building better, more reliable infrastructure at scale. I share my thoughts and write about my learnings on medium. https://medium.com/@dhanwanthvarala

Experience

8 mos

Total Experience

8 mos

Average Tenure

8 mos

Current Experience

Vaaluka solutions

2 roles

Design Verification Engineer

Jul 2025 – Aug 2025 · 1 mo · Hyderabad, Telangana, India · On-site

I have developed and implemented complete UVM testbenches from scratch—including agents, scoreboards, and virtual sequences—for complex IPs such as Aligner, SPI Master, and AXI DMA. My work involved verifying high-performance bus structures and peripheral protocols like AXI, APB, and SPI, where I consistently achieved 100% functional and code coverage through rigorous testing. I utilized RAL models for advanced register verification, implementing frontdoor and backdoor access sequences to ensure hardware integrity. To scale these efforts, I built automated regression flows using Makefiles and random seeds, enabling efficient validation of complex RTL designs and FSMs. Throughout these projects, I systematically debugged critical logic issues using waveform analysis in ModelSim and Questa to ensure rock-solid hardware performance.

SystemVerilogUniversal Verification Methodology (UVM)Debugging