Arindam Chatterjee

Software Engineer

Bengaluru, Karnataka, India12 yrs 7 mos experience

Highly Stable

Key Highlights

Expert in RTL Design and Microarchitecture.
Proven track record in CPU subsystem design.
Strong experience in functional verification and automation.

Stackforce AI infers this person is a highly skilled RTL Design and Verification Engineer in the semiconductor industry.

Contact

Skills

Core Skills

Rtl DesignMicroarchitectureFunctional VerificationVerification

Other Skills

CPU pipelineLoad Store unit RTL designArm DynamIQ Shared UnitAMBA AXIAPBATB interfacesdebuggingbringupMicroarchitectingDesigning Low power featuresSilicon debuggingAutomation using perlGatesimPPA runs automationAssertion automation

About

Interested to work in: RTL Designing and Microarchitecture of complex IPs

Experience

12 yrs 7 mos

Total Experience

2 yrs 9 mos

Average Tenure

1 yr 6 mos

Current Experience

Amd

Senior Member of Technical Staff

Nov 2024 – Present · 1 yr 6 mos · Bengaluru, Karnataka, India · Hybrid

CPU pipeline, Load Store unit RTL designer

CPU pipelineLoad Store unit RTL designRTL Design

Arm

Staff Design Engineer

May 2022 – Nov 2024 · 2 yrs 6 mos · Bengaluru, Karnataka, India

Part of Arm DynamIQ Shared Unit(L3 cache controller) Team.
Experience in AMBA AXI, APB, ATB interfaces.
Experience in developing micro-architecture, RTL design, debugging and bringup.

Arm DynamIQ Shared UnitAMBA AXIAPBATB interfacesmicro-architectureRTL design+3

Qualcomm

3 roles

Staff Design Engineer

Nov 2021 – Apr 2022 · 5 mos

Senior Lead Design Engineer

Promoted

Nov 2019 – Nov 2021 · 2 yrs

Microarchitecting and Designing the Low power features of CPU subsystem
Silicon debugging for the first ARM V9 based chip
Overall lead for CPU subsystem

MicroarchitectingDesigning Low power featuresSilicon debuggingMicroarchitecture

Senior Design Engineer

Apr 2017 – Oct 2019 · 2 yrs 6 mos

Contributed to
1) Automation using perl
Gatesim,PPA runs automation, Assertion automation.
2) RTL Designing
Rendering ARM RTL . Designed various CPU subsystem feature/bug fixes.
Design compliance with various linting tools, CDC, PLDRC, DC synth flow etc.
Mbist RTL insertion
3) Verification
GCC assembler bringup for subsystem.

Automation using perlGatesimPPA runs automationAssertion automationRTL DesigningDesign compliance+9

Intel corporation

Pre-Si Verification Engineer

Oct 2016 – Mar 2017 · 5 mos · Bengaluru Area, India

Contributed towards soc level verification of UFS controller.
1) Contributed towards integrating UFS subsytem and brought up the basic data path.
2)Porting testcases from IP level and also writing soc level testcases for measuring clock frequencies and routing of interrupts.
3)Power aware verification using UPF.

soc level verificationUFS controllerintegrating UFS subsystemwriting soc level testcasesPower aware verificationFunctional Verification

Samsung electronics

2 roles

Senior Hardware Engineer

Promoted

Jan 2015 – Sep 2016 · 1 yr 8 mos

1)Mipi MPHY Verification
2)Mipi UNIPRO Verification
3)Jedec UFS Verification
4)QSPI Serial Flash Verification
5)QChannel UVC development
Exposure to designing all verification components from scratch. Bringing up test framework. Connecting Cadence VIPs. Writing and debugging testcases.

Mipi MPHY VerificationMipi UNIPRO VerificationJedec UFS VerificationQSPI Serial Flash VerificationQChannel UVC developmentVerification

Hardware engineer

Jun 2013 – Jan 2015 · 1 yr 7 mos

Joined as a part of Cpu verification team.
1) Assembly test writing and debugging.
2) Writing basic checkers in system verilog.
3) Also Been a part of the MCA (Machine Check Architecture) feature verification for the same project.

Assembly test writingdebuggingwriting basic checkersSystem VerilogMCA feature verificationVerification