Mufaddal Saifee — CTO

Results-driven Digital IC Design Leader with a track record of spearheading complex silicon projects and site establishment (SiFive Ahmedabad). Deep expertise in Network-on-Chip (NoC), cache coherency, and processor architecture. EXPERIENCE & LEADERSHIP HIGHLIGHTS: * Site Lead, Ahmedabad (SiFive): Spearheaded the successful establishment and growth of SiFive's Ahmedabad site, building a foundational presence and fostering local team development. * Network-on-Chip (NoC) Leadership: Led SiFive's comprehensive Network-on-Chip (NoC) efforts, from architecture and microarchitecture to implementation and verification, including developing a NoC tool (JSON-to-RTL, automated verification environment). * Protocol Bridge Architecture & Implementation: Architected and led team to design and verify high-performance protocol bridges for native non-coherent, credit-based interconnects, for Provino and Google. CORE TECHNICAL EXPERTISE: * Digital IC Design Flow: Proficient across the complete digital IC design lifecycle: architectural definition, macro/micro-architecture, RTL coding (VHDL, Verilog), synthesis, Place & Route (PAR), Static Timing Analysis (STA) for ASIC/FPGA, and robust verification. * Interconnect & Coherency Specialist: • AMBA Expertise: Specialist in AMBA non-coherent interconnects (ACE-Lite, AXI, AHB, APB, AXI4Stream, Low-power P & Q, TrustZone, Coresight). Designed and developed AMBA V1-5 compliant initiator/target bridges for credit-based NoCs. • Cache Coherency: Highly skilled in cache coherent protocols (TileLink2, ACE, CHI), with extensive knowledge of coherency implementation, cache controllers, and home node designs. * Processor & IP Development: • Diverse Processor Implementations: Extensive experience implementing diverse processors: ARM VFP-2 compliant (Single/Double Precision Vector Floating Point), Application-Specific G-code CISC for CNC, Low-power 32-bit RISC, Application-Specific RISC for PLCs, and Application-Specific Generic Timing Signal Generators. • Complex IP Cores: Proven experience in designing and implementing complex IP cores, such as IEEE 754 Floating Point Arithmetic Units, BLDC Motor Control, and IEEE 802.3 compliant 10G MAC. • Algorithm Design: Designed and implemented complex algorithms, including 3D Linear Interpolation, 2D Circular Interpolation, IDEA Encryption/Decryption, and PID control. * FPGA Engineering: Comprehensive FPGA (Altera and Xilinx) engineering experience with soft-core processor (MicroBlaze) based system development.

Stackforce AI infers this person is a Digital IC Design expert with strong leadership in semiconductor and hardware development.

Location: Ahmedabad, Gujarat, India

Experience: 17 yrs 11 mos