Munish Kumar

Director of Engineering

Bangalore, Karnataka, India24 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

23+ years of experience in SoC Power Delivery.
Led 30+ successful SoC PRQ/Tapeouts.
Expert in managing multi-site design teams.

Stackforce AI infers this person is a Semiconductor Engineering expert with extensive experience in power delivery and SoC design.

Contact

Skills

Core Skills

SocPower DeliveryAnalog

Other Skills

SoC Power DeliveryPower Integrity simulationsPower OptimizationFIVR IntegrationAnalog IP IntegrationMixed SignalVLSICircuit DesignCMOSPLLAnalog Circuit DesignMicroprocessorsICApplication-Specific Integrated Circuits (ASIC)Very-Large-Scale Integration (VLSI)

About

23+ years of experience with specialization in SoC/System Power Delivery (PDN, IR/RV, ESD), Power estimation and optimization, on-die power delivery circuits and analog IP integration with a demonstrated track record of 30+ SoCs successful PRQ/Tapeout of high end server/laptop/desktop, IoTG, Modem and Low Power Mobile chip designs. Excellence in managing multi-site design teams, creating goal-oriented vision for business development with track record of great achievement to meet aggressive schedules without compromising design quality

Experience

24 yrs 2 mos

Total Experience

8 yrs

Average Tenure

20 yrs 3 mos

Current Experience

Intel corporation

2 roles

Senior Director of Engineering

Promoted

Jul 2025 – Present · 9 mos

Director Engineering

Dec 2005 – Jun 2025 · 19 yrs 6 mos

SoC Power Delivery (PDN/IR/RV), ESD Convergence and Sign Off
Managing the team for driving SoC level PDN, IR/RV & ESD convergence and sign-off for high performance and low power SoCs
Driving system and SoC level power delivery solutions to optimize Power, Perf and BOM cost
Optimize power delivery architecture (FIVR/PMIC/PGs/PSWs) to achieve best in class PPA
Product definition for Power grids, power gating, bump planning, static and dynamic IR drop methodology, reliability checks, Inrush simulations etc.
Power Integrity simulations at system level
SoC Power Sign Off
SoC Power Optimization, Convergence and Sign Off: Leading backend/RTL SoC power optimization, convergence and Sign off to achieve best in class PPA for low power SoC design
Leading the Technical work groups to collaborate with power architect, FE Team, PnP team to achieve best in class SoC power
FIVR (Fully Integrated Voltage Regulator)/Analog Integration
FIVR Integration and System level Simulations: Leading FIVR BE Physical Integration and system level simulations for all Client/Server SoCs. Driving on-die/pkg/Inductor optimization to meet design specs e.g. efficiency, stability, ripple and droop
Analog IP Integration: Driving analog IP integration and sign off for various SoCs. Define and Coordinate product landing zone and IP Specification requirements with IP teams and integrating them into SoC
Strategic Rotation to build Power delivery (FIVR) Expertise in Intel India (Intel Corporation, Hillsboro, OR, USA, May 2010 – March 2011)
Nominated for 1-year strategic rotation program at Intel Oregon to gain expertise in power delivery and to ensure flawless design and Integrations of FIVRs for high performance SoCs

SoC Power DeliveryPower Integrity simulationsPower OptimizationFIVR IntegrationAnalog IP IntegrationSoC+1

Texas instruments india pvt ltd

Design Engineer

Apr 2004 – Dec 2005 · 1 yr 8 mos · Bengaluru Area, India

As a Design Engineer responsibilities were to define I2C and Programmable LVCMOS IO architecture based on specifications, circuit design, simulations and involvement in reviews.