Jhansi Nallapati — Software Engineer
With over a decade of experience in the semiconductor industry, currently serving as Senior Member of Technical Staff at AMD, specializing in Design-for-Test (DFT) methodologies, including MBIST, scan insertion, and simulation debugging. Contributed to advancing the organization’s testing frameworks and ensuring first time silicon pass. Passionate about delivering scalable and efficient DFT architectures, fostering collaboration across teams to meet critical project milestones. Committed to aligning technical expertise with organizational goals to drive innovation and improve product quality.
Stackforce AI infers this person is a semiconductor industry expert with a focus on DFT methodologies and silicon validation.
Location: Hyderabad, Telangana, India
Experience: 13 yrs 7 mos
Skills
- Dft Architecture Planning
- Silicon Validation
Career Highlights
- Over a decade of semiconductor industry experience
- Expert in Design-for-Test methodologies
- Proven track record of first-time silicon pass
Work Experience
AMD
SMTS -- Silicon design engineer (6 mos)
INVECAS
Sr. principal design engineer (4 yrs 7 mos)
Member Of Technical Staff (1 yr 1 mo)
Soctronics
Member Of Technical Staff (9 mos)
Senior Design Engineer (2 yrs 11 mos)
Design Engineer (1 yr 8 mos)
engineer trainee (11 mos)
PENTAGON RUGGED SYSTEMS (INDIA) PRIVATE LIMITED
Design Engineer (1 yr 3 mos)
Electronics Corporation of India Limited (ECIL), Department of Atomic Energy, Government of India.
Trainee (1 yr)
Education
M.tech at JNTUH College of Engineering Hyderabad
industrial training at vedaiit
B.tech at Vignana Bharathi Institute of Technology
Diploma of Education at s.v.govt.polytechnic college
high school at Chaitanya bala kuteer