Jhansi Nallapati

Software Engineer

Hyderabad, Telangana, India13 yrs 7 mos experience
Highly Stable

Key Highlights

  • Over a decade of semiconductor industry experience
  • Expert in Design-for-Test methodologies
  • Proven track record of first-time silicon pass
Stackforce AI infers this person is a semiconductor industry expert with a focus on DFT methodologies and silicon validation.

Contact

Skills

Core Skills

Dft Architecture PlanningSilicon Validation

Other Skills

MBIST and Scan insertionsimulation debugboundaryscan insertion and validationIJTAG networkAutomatic Test Pattern Generation (ATPG)

About

With over a decade of experience in the semiconductor industry, currently serving as Senior Member of Technical Staff at AMD, specializing in Design-for-Test (DFT) methodologies, including MBIST, scan insertion, and simulation debugging. Contributed to advancing the organization’s testing frameworks and ensuring first time silicon pass. Passionate about delivering scalable and efficient DFT architectures, fostering collaboration across teams to meet critical project milestones. Committed to aligning technical expertise with organizational goals to drive innovation and improve product quality.

Experience

13 yrs 7 mos
Total Experience
3 yrs 3 mos
Average Tenure
6 mos
Current Experience

Amd

SMTS -- Silicon design engineer

Oct 2025Present · 6 mos · India · On-site

MBIST and Scan insertionDFT architecture planningsimulation debugboundaryscan insertion and validationIJTAG networkAutomatic Test Pattern Generation (ATPG)+1

Invecas

2 roles

Sr. principal design engineer

Promoted

Feb 2021Sep 2025 · 4 yrs 7 mos

Member Of Technical Staff

Feb 2021Mar 2022 · 1 yr 1 mo

Soctronics

4 roles

Member Of Technical Staff

Apr 2020Jan 2021 · 9 mos · Hyderabad, Telangana, India · On-site

Senior Design Engineer

Promoted

Apr 2017Mar 2020 · 2 yrs 11 mos · Hyderabad, Telangana, India · On-site

Design Engineer

Jul 2015Mar 2017 · 1 yr 8 mos · Hyderabad, Telangana, India · On-site

engineer trainee

Jul 2014Jun 2015 · 11 mos · Hyderabad, Telangana, India · On-site

Pentagon rugged systems (india) private limited

Design Engineer

Sep 2012Dec 2013 · 1 yr 3 mos · Hyderabad, Telangana, India · On-site

Electronics corporation of india limited (ecil), department of atomic energy, government of india.

Trainee

Aug 2011Aug 2012 · 1 yr · Hyderabad, Telangana, India · On-site

Education

JNTUH College of Engineering Hyderabad

M.tech — ES & VLSI

Nov 2014Jan 2017

vedaiit

industrial training — VLSI

Jan 2014Jun 2014

Vignana Bharathi Institute of Technology

B.tech

Jun 2008Apr 2011

s.v.govt.polytechnic college

Diploma of Education — Biomedical/Medical Engineering

Jun 2004Dec 2007

Chaitanya bala kuteer

high school — schooling

Jun 2003Mar 2004

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