M

Mamatha S

Product Engineer

Hyderabad, Telangana, India3 yrs 6 mos experience
Most Likely To Switch

Key Highlights

  • Experienced in SystemVerilog and UVM methodologies.
  • Proven track record in verification engineering roles.
  • Strong foundation in AXI and APB protocols.
Stackforce AI infers this person is a Verification Engineer specializing in digital design and verification within the semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

SystemverilogUniversal Verification Methodology (uvm)

Other Skills

AXI ProtocolAPB ProtocolEthernet Mac IP VerificationSystem verilog

Experience

3 yrs 6 mos
Total Experience
1 yr 9 mos
Average Tenure
2 yrs 9 mos
Current Experience

Amd

Design and Verification Engineer

Jul 2023 – Present · 2 yrs 9 mos · Hyderabad, Telangana, India · On-site

System verilogAXI ProtocolAPB ProtocolSystemVerilogUniversal Verification Methodology (UVM)Ethernet Mac IP Verification

Scaledge technology

2 roles

Verification Engineer

Sep 2022 – Jun 2023 · 9 mos · Bengaluru, Karnataka, India

Universal Verification Methodology (UVM)Ethernet Mac IP Verification

ASIC Verification Intern

Mar 2022 – Sep 2022 · 6 mos · Bengaluru, Karnataka, India

Universal Verification Methodology (UVM)AXI Protocol

Education

Sri Venkateshwara College of Engineering, BANGALORE

Bachelor of Engineering - BE — electronics and communication

Jan 2018 – Jan 2022

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