Subbulakshmi S

Product Manager

Bengaluru, Karnataka, India11 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 9+ years in PDK/CSD design with extensive tool expertise.
  • Created multi fab compatible generic pcell for 28nm process.
  • Automated QRC extraction setup, improving efficiency.
Stackforce AI infers this person is a semiconductor design engineer with expertise in PDK and CAD methodologies.

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Skills

Core Skills

EdaPdkLayout Design

Other Skills

SKILL programmingEMIRPerlManagementLeadershipsvrfPython (Programming Language)Layout Versus Schematic (LVS)Design Rule Checking (DRC)pcell designComputer-Aided Design (CAD)PDK DevelopmentCadence VirtuosoADEPhysical verification

About

• Have 9+ years of experience in PDK/CSD design. Have expertise in layout related concepts like matching, shielding, symmetrical layout, placement, floorplan, routing. Have debugged involved simulation performance issue. • Have worked with all planar, FINFET, GAA and FDSOI process. Have worked with TSMC,SAMSUNG,GF,UMC,SMIC and Intel process and process nodes 28 and below. • Tools knowledge: GTE,PAS, EMX, PEGASUS,PVS,VIRTUOSO,QUANTUS,QRC,SPECTRE ASSEMBLER, Voltus-Fi, STEP • Expertise in creating custom methodology pcells for process SEC8,SEC14,SEC10,SCE7,GF12,SEC4,intel 22 and 18 nodes. Created MOS, stack mos, PolyspcerRX, TAP, Resistor and Vncap pcells following template size with XL features and abutment. • Created multi fab compatible generic pcell for 28nm process which could be used for TSMC28,UMC28,SMIC28,GF28 and Samsung FDSOI 28nm process. • Expertise in QRC/Extraction setup and automation. Supporting for all QRC related issues (performance, usage and tool related issues) for all samsung, tsmc, intel and GF nodes. Automation done for BEOL comparison, for validating double counting of parasitics and flag setting of pre & post layout simulation. Validation of collateral files. Automation for Layout dependent effects. creation of Batch mode extraction script. • Automation for layout area efficiency calculation for lower nodes. Helped to reduce area by 30% for bandgap block in T16. • Developed a schematic/layout migration script. Ported layout database retaining XL connectivity, abutment and multi-stack compatibility. • Have done setup and support for EMIR and lightning. Automation for EMIR QA. • Created custom scripts for point to point resistance calculation, layout database porting, custom via creation, to compare PDKS, pcells. • Involved in recruitment process and have trained interns and new employees • Possess excellent technical, interpersonal, and analytical skills.

Experience

11 yrs 7 mos
Total Experience
6 yrs 11 mos
Average Tenure
11 yrs 7 mos
Current Experience

Nvidia

Senior cad engineer

Feb 2024Present · 2 yrs 2 mos

Cadence design systems

5 roles

Principal CAD/PDK Design engineer

Promoted

Jul 2023Present · 2 yrs 9 mos

Lead CAD/PDK Design Engineer

Oct 2020Jun 2023 · 2 yrs 8 mos

EDAPDKSKILL programmingEMIRPerl

Senior CAD/PDK Design Engineer

Promoted

Jul 2018Sep 2020 · 2 yrs 2 mos

CAD/PDK Design Engineer

Jan 2015Jun 2018 · 3 yrs 5 mos

Analog layout Intern

Jun 2014Jan 2015 · 7 mos

  • Created layout for bandgap. Learned matching, shielding, symmetrical layout, floor planning, placement and area optimization. Developed custom scripts for layout migration.
Layout DesignSKILL programmingPerl

Procyon techsolutions

Intern

Jan 2014Mar 2014 · 2 mos · Bangalore,India

Education

Birla Institute of Technology and Science, Pilani

Master of Technology - MTech — Microelectronics

Jan 2017Jan 2019

Mepco Schlenk Engineering College

Bachelor of Engineering (B.E.) — Electronics and Communications Engineering

Jan 2010Jan 2014

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Subbulakshmi S - Product Manager | Stackforce