Subbulakshmi S — Product Manager
• Have 9+ years of experience in PDK/CSD design. Have expertise in layout related concepts like matching, shielding, symmetrical layout, placement, floorplan, routing. Have debugged involved simulation performance issue. • Have worked with all planar, FINFET, GAA and FDSOI process. Have worked with TSMC,SAMSUNG,GF,UMC,SMIC and Intel process and process nodes 28 and below. • Tools knowledge: GTE,PAS, EMX, PEGASUS,PVS,VIRTUOSO,QUANTUS,QRC,SPECTRE ASSEMBLER, Voltus-Fi, STEP • Expertise in creating custom methodology pcells for process SEC8,SEC14,SEC10,SCE7,GF12,SEC4,intel 22 and 18 nodes. Created MOS, stack mos, PolyspcerRX, TAP, Resistor and Vncap pcells following template size with XL features and abutment. • Created multi fab compatible generic pcell for 28nm process which could be used for TSMC28,UMC28,SMIC28,GF28 and Samsung FDSOI 28nm process. • Expertise in QRC/Extraction setup and automation. Supporting for all QRC related issues (performance, usage and tool related issues) for all samsung, tsmc, intel and GF nodes. Automation done for BEOL comparison, for validating double counting of parasitics and flag setting of pre & post layout simulation. Validation of collateral files. Automation for Layout dependent effects. creation of Batch mode extraction script. • Automation for layout area efficiency calculation for lower nodes. Helped to reduce area by 30% for bandgap block in T16. • Developed a schematic/layout migration script. Ported layout database retaining XL connectivity, abutment and multi-stack compatibility. • Have done setup and support for EMIR and lightning. Automation for EMIR QA. • Created custom scripts for point to point resistance calculation, layout database porting, custom via creation, to compare PDKS, pcells. • Involved in recruitment process and have trained interns and new employees • Possess excellent technical, interpersonal, and analytical skills.
Stackforce AI infers this person is a semiconductor design engineer with expertise in PDK and CAD methodologies.
Location: Bengaluru, Karnataka, India
Experience: 11 yrs 7 mos
Skills
- Eda
- Pdk
- Layout Design
Career Highlights
- 9+ years in PDK/CSD design with extensive tool expertise.
- Created multi fab compatible generic pcell for 28nm process.
- Automated QRC extraction setup, improving efficiency.
Work Experience
NVIDIA
Senior cad engineer (2 yrs 2 mos)
Cadence Design Systems
Principal CAD/PDK Design engineer (2 yrs 9 mos)
Lead CAD/PDK Design Engineer (2 yrs 8 mos)
Senior CAD/PDK Design Engineer (2 yrs 2 mos)
CAD/PDK Design Engineer (3 yrs 5 mos)
Analog layout Intern (7 mos)
Procyon TechSolutions
Intern (2 mos)
Education
Master of Technology - MTech at Birla Institute of Technology and Science, Pilani
Bachelor of Engineering (B.E.) at Mepco Schlenk Engineering College