Shruti Dixit

Engineering Manager

Bengaluru, Karnataka, India22 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Experienced in RTL design and verification.
Proficient in FPGA design and prototyping.
Strong background in managing engineering teams.

Stackforce AI infers this person is a seasoned engineering manager with expertise in RTL design and FPGA technologies.

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Skills

Core Skills

Rtl DesignVerificationFpga Design

Other Skills

RTLSynthesisFormal verificationSTAConstraints generationTiming ClosureECOsSynopsys VCSDesign compilerPrimetime-SIFormalityPerltclSystem VerilogVMM methodology

Experience

22 yrs 2 mos

Total Experience

3 yrs 8 mos

Average Tenure

4 yrs 10 mos

Current Experience

Intel corporation

Engineering Manager

Jun 2021 – Present · 4 yrs 10 mos

Openfive

Sr staff Engineer II

Jan 2020 – Jun 2021 · 1 yr 5 mos

Seagate technology

2 roles

Sr Staff Engineer

Promoted

Oct 2017 – Jan 2020 · 2 yrs 3 mos · Pune Area, India

Staff Engineer

Nov 2014 – Oct 2017 · 2 yrs 11 mos · Pune Area, India

Lsi corporation

2 roles

Design Engineer, Staff

Promoted

Mar 2013 – Nov 2014 · 1 yr 8 mos

Design Engineer, Senior

Apr 2010 – Mar 2013 · 2 yrs 11 mos

Wipro technologies

Module Leader.

Jan 2007 – Apr 2010 · 3 yrs 3 mos

RTL, Synthesis, Formal verification, STA, Constraints generation, Timing Closure and ECOs.
Worked on chips implemented in 130, 90 and 45nm with complex clock structures.
Hands on knowledge of Synopsys VCS, Design compiler, Primetime-SI, Formality. Perl, tcl.

RTLSynthesisFormal verificationSTAConstraints generationTiming Closure+9

Sasken communication technologies ltd

Design Engineer.

Jan 2004 – Dec 2006 · 2 yrs 11 mos

Verification enviornment developement using system verilog and VMM methodology, System verilog assertions.
Worked on Synopsys VCS, VMM.
Design Validation, FPGA prototyping, FPGA design. Hands-on knowledge of Xilinx and altera tools.
Worked on VHDL, Verilog.

System VerilogVMM methodologySystem Verilog assertionsDesign ValidationFPGA prototypingFPGA design+6