D

Deepak Joice

CEO

Bengaluru, Karnataka, India18 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in complex SOC floor planning and design.
Experience with advanced technology nodes from 28nm to 4nm.
Proficient in multi-power and multi-voltage domain designs.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in SOC architecture and physical design.

Contact

Skills

Core Skills

Physical DesignSystem On A Chip (soc)

Other Skills

Clock Tree SynthesisPlacement and routingVery-Large-Scale Integration (VLSI)Application-Specific Integrated Circuits (ASIC)FloorplanningTCLPlace & RouteCadence EncounterCadence Innovus

About

Experienced Physical design Engineer with a history of working in multiple SOCs. - Expertise in top level complex SOC floor planning including hierarchical partitioning, pin placement, IP integration, IO planning and bump routing. - Expertise in SOC/Block level place & route, CTS and ECO implementation. - Worked in advanced technology nodes ranging from 28nm to 4nm, multi-million gate, multi power-multi voltage domain designs.

Experience

18 yrs 1 mo

Total Experience

6 yrs

Average Tenure

9 yrs 11 mos

Current Experience

Qualcomm

4 roles

Principal Engineer/Manager

Promoted

Dec 2025 – Present · 4 mos

Physical DesignClock Tree SynthesisPlacement and routingVery-Large-Scale Integration (VLSI)Application-Specific Integrated Circuits (ASIC)System on a Chip (SoC)+5

Engineer, Sr Staff/Mgr

Promoted

Dec 2021 – Dec 2025 · 4 yrs

Staff Engineer

Nov 2017 – Nov 2021 · 4 yrs

Senior Lead Engineer

Apr 2016 – Nov 2017 · 1 yr 7 mos

Mediatek

Staff Engineer

Apr 2015 – Mar 2016 · 11 mos · Bengaluru, Karnataka, India

Wipro limited

Technical Lead

Jan 2008 – Apr 2015 · 7 yrs 3 mos · Bengaluru, Karnataka, India

Education

Cochin University of Science and Technology

Master of Technology (M.Tech.)

Jan 2007 – Present

Govt. College of Engineering, Kannur

Bachelor of Technology - BTech — Electronics and Communications Engineering

Govt. College of Engineering, Kannur

Bachelor of Technology - BTech — Electonics and Communication

Stackforce found 100+ more professionals with Physical Design & System On A Chip (soc)

Explore similar profiles based on matching skills and experience

Shubhankar Das

Lead Engineer

at Qualcomm

Faridabad, India10 yrs 1 mo exp

Pritender Singh

Principal Design Engineer

at TSMC

Kanata, Canada17 yrs 4 mos exp

ASICEmbedded SystemsVLSI

mahaboob patan

Principal Engineer

at Intel Corporation

Bengaluru, India17 yrs 9 mos exp

Full Chip IntegrationLayout Design

DEEPU JOSE

Principal Physical Design Engineer

at Allegro MicroSystems

Edinburgh, United Kingdom12 yrs 9 mos exp

Nivethitha A

Senior Engineer

at Synopsys Inc

Bengaluru, India5 yrs exp

VerilogFloorplanningField-Programmable Gate Arrays (FPGA)

Gaurav Goyal

Technical Director

at NXP Semiconductors

Bengaluru, India17 yrs 8 mos exp

Haripriya K R

ASIC Engineer

at NVIDIA

Ananthapuramu, India5 yrs 7 mos exp

Application-Specific Integrated Circuits (ASIC)Very-Large-Scale Integration (VLSI)Low Power ChecksLayout Verification

Abhishek Jain

Senior Staff Manager

at Qualcomm

Delhi, India23 yrs 4 mos exp

Functional VerificationUVMEthernetTestbench DevelopmentValidation