Saniya K.

DevOps Engineer

Bengaluru, Karnataka, India7 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in UWB SoC Verification and IP Development.
Led a team for Intel PCH SoC chipsets verification.
Proficient in developing complex verification environments.

Stackforce AI infers this person is a Verification Engineer specializing in SoC and IP verification within the semiconductor industry.

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Skills

Core Skills

VerificationSoc VerificationIp VerificationVerification Ip Development

Other Skills

UWB SoC VerificationVerification of Intel PCH SoC chipsetsTestbench bringupTeam managementIP level VerificationFPGA based VerificationSV-UVM Verification Environment developmentSystem/IP level VerificationAMBA APB protocolVCS Save/RestoreAssertion Based VerificationGitVerilogVHDLPython

About

Languages : System Verilog, Verilog, C Methodology: UVM, OVM, Saola (Intel) Protocols: Ethernet, AMBA APB, AMBA AXI, AMBA AHB, gPTP, MIPI, PCIe, UWB IEEE standards: IEEE 802.3 (MII/GMII/XGMII), IEEE 802.1Q (VLANs), IEEE 1588 (PTP), IEEE 802.11 (Ethernet-MAC), IEEE 802.15.4 (UWB Frames) Tools Used: Cadence Xcelium, Synopsis Verdi, VCS, DVE, DVT, VCF, vManager, Git Scripting Language: Shell, Perl, TCL Platform : Linux, Unix and windows Experienced in - Verification Environment & Components Architecture Development - Constraint Random Verification and Assertion Based Verification using SVA. - Memory model development - VIP Integration - Development of Verification IP adhering AMBA APB protocol - Functional & Code Coverage Analysis, coverage metrics and Closure - UVM RAL/Register Model Implementation & Usage - Worked on Synopsis VCS Save/Restore

Experience

7 yrs 6 mos

Total Experience

2 yrs 6 mos

Average Tenure

3 yrs 11 mos

Current Experience

Nxp semiconductors

Digital Verification Engineer - Lead

May 2022 – Present · 3 yrs 11 mos · Bengaluru, Karnataka, India

UWB SoC Verification

UWB SoC VerificationVerification

Intel corporation

Senior Engineer (SoC Verification) - CW

May 2021 – May 2022 · 1 yr · Bengaluru, Karnataka, India

Worked on Verification of the Intels PCH SoC chipsets, Lead a team of 5 members, Worked on Testbench bringup and Legacy Projects, managed teams day-to-day activities and guided them wherever required and reported directly to client

Verification of Intel PCH SoC chipsetsTestbench bringupTeam managementSoC Verification

Tata elxsi

2 roles

Senior Engineer (IP/ASIC Verification)

Promoted

Oct 2020 – May 2021 · 7 mos · Bangalore Urban, Karnataka, India

IP level, FPGA based Verification
Verification Planning which includes the Feature Extraction, Test plan, Coverage plan, Stimulus plan, Checker plan development and traceability
SV, SV-UVM Verification Environment development
Shell script development for standalone/regression simulations
Writing directed/random testcases as per test plan
Debugging, Writing coverage and assertions
Discussions with client to fix ENV/RTL issues or update if any changes on RTL
Stability, Coverage metrics and closure

IP level VerificationFPGA based VerificationSV-UVM Verification Environment developmentIP Verification

Engineer (IP/ASIC Verification)

Sep 2018 – Sep 2020 · 2 yrs · Bangalore Urban, Karnataka, India

Verification IP development, System/IP level Verification
VIP development adhering to AMBA APB protocol
Verification Planning which includes the Feature Extraction, Test plan, Coverage plan, Stimulus plan, Checker plan development and traceability
Verification Environment development using System Verilog and UVM1.2 methodology
Writing directed/random testcases as per test plan
Debugging, Writing coverage and assertions.
Stability, Coverage metrics and closure

Verification IP developmentSystem/IP level VerificationAMBA APB protocolVerification IP Development