Payal Joshi

Software Engineer

Bengaluru, Karnataka, India9 yrs 8 mos experience

Highly Stable

Key Highlights

Expert in DDR and DFI protocol verification.
Proficient in Universal Verification Methodology.
Experienced in silicon design and hardware engineering.

Stackforce AI infers this person is a semiconductor verification engineer with expertise in DDR protocols.

Contact

Skills

Other Skills

DDRSVUniversal Verification Methodology (UVM)IP VERIFICATIONFunctional Verification

About

Working as DDR PHY Verification Engineer.Having knowledge of DDR and DFI protocol

Experience

9 yrs 8 mos

Total Experience

5 yrs 11 mos

Average Tenure

3 yrs 9 mos

Current Experience

Amd

2 roles

MTS Verification Engineer

Jul 2025 – Present · 9 mos

Senior silicon design engineer

Jul 2022 – Present · 3 yrs 9 mos

Samsung r&d institute india - bangalore private limited

2 roles

Senior Hardware Engineer

Jul 2017 – Jul 2022 · 5 yrs · Bengaluru, Karnataka, India

Intern

Jun 2016 – May 2017 · 11 mos · Bengaluru, Karnataka, India

Education

Veermata Jijabai Technological Institute (VJTI)

Master of Technology - MTech — Electronics

Jan 2015 – Jan 2017

P.R.Patil College of Engineering & Technology, Gajanan Township Campus, Kathora Road,Amravati

B.E — Electronics and Communications Engineering

Jan 2009 – Jan 2013

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