Suresh kola

Software Engineer

Bengaluru, Karnataka, India15 yrs experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 3 years of experience in Physical Design.
  • Expertise in advanced technology nodes from 5nm to 65nm.
  • Proficient in EDA tools and scripting for automation.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and EDA tools.

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Skills

Core Skills

Physical DesignAsicSoc

Other Skills

Physical VerificationLow-power DesignSynthesisTiming ClosureLayout Versus Schematic (LVS)System on a Chip (SoC)Static Timing AnalysisPlace & RouteLogic DesignSystemVerilogFunctional VerificationFloorplanningDRCRTL designLVS

About

A seasoned technology executive with more than 3+ years of industrial experience. Currently associating with Qualcomm Semiconductors, Bangalore as Physical Design Engineer. Worked in very aggressive schedules in various projects.Ready to go extra mile for achieving the destination. Having experience in product & service based industry. Very Comfortable from the floor-planning to verification. Added to all, interest to script & develop the flow automation. Technically proficient with proven ability to communicate effectively and deliver on-time technical solutions to maximize business value. Expertise: * Good knowledge in the Physical Design Flow. * Worked with various technology from 5nm to 65nm. * Hands on experience on various Fabs such as GF and TSMC. * Performed Floorplaning, Clock Tree Synthesis, Static Timing Analysis and SI driven routing. * Experience in the Xtalk (using Celtic), Antenna Fixes, LEC(using Formality) & IR Drop analysis. * Performed Floor-planing, Placement & Physical Verification * Scripting : TCL & perl EDA Expertise: * Worked on Various Industry Standard Tools Like SoC Encounter, IC Compiler, PrimeTime, ETS, Celtic, Formality, Caliber, Hercules,Design Compiler, Formality & CalDRV.

Experience

15 yrs
Total Experience
2 yrs 6 mos
Average Tenure
3 yrs 7 mos
Current Experience

Amd

SMTS Silicon Design Engineer

Sep 2022Present · 3 yrs 7 mos · Bengaluru, Karnataka, India

  • CPU Cores Team (Decoder Unit Lead)
Physical DesignPhysical VerificationLow-power DesignSynthesisTiming ClosureLayout Versus Schematic (LVS)+1

Samsung electronics

Senior Staff Engineer

Jun 2019Sep 2022 · 3 yrs 3 mos · India

Physical VerificationPhysical DesignLow-power DesignSystem on a Chip (SoC)SoC

Mediatek

Staff Engineer

May 2016Jun 2019 · 3 yrs 1 mo · Singapore

Physical DesignLow-power DesignStatic Timing Analysis

Ust global

Senior Physical Design Engineer consultant at Intel

Mar 2015May 2016 · 1 yr 2 mos · Penang, Malaysia

Physical DesignStatic Timing Analysis

Sicon design technologies pvt. ltd.

Physical Design Engineer consultant at Qualcomm&AMD

Dec 2011Feb 2015 · 3 yrs 2 mos · Bengaluru, Karnataka, India

SynthesisPhysical Design

Defence research and development organisation (drdo)

Physical Design Engineer( Internship)

Jun 2009Mar 2010 · 9 mos · Hyderabad Area, India

Education

GITAM Deemed University

M.Tech — VLSI DESIGN

Jan 2008Jan 2010

Jawaharlal Nehru Technological University

B.Tech — Electronics and Communication Engineering

Jan 2003Jan 2007

Srichaitanya junior college

Junior Inter — M.P.C

Jan 2001Jan 2003

B.V.K School

10th class — SSC

Jan 2000Jan 2001

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