Siva Prasad Tanikonda — Software Engineer
7+ Years of experience in IP verification. Hands on Experience in constrained-random and coverage-driven IP level verification using SystemVerilog, UVM Hands on Expertize in developing test bench infrastructure for IP level using UVM methodology Worked on functional coverage and code coverage Protocol Knowledge on SPI, AXI4, Ethernet & RDMA. Worked on SerDes project. Worked on RDMA protocol.
Stackforce AI infers this person is a VLSI verification engineer with expertise in ASIC design and verification methodologies.
Location: Andhra Pradesh, India
Experience: 7 yrs 2 mos
Skills
- System Verilog
- Uvm
Career Highlights
- 7+ years of experience in IP verification.
- Expert in UVM methodology for test bench development.
- Proficient in functional and code coverage analysis.
Work Experience
AMD
Sr Silicon Design Engineer (1 yr 9 mos)
Silicon Design Engineer 2 (1 yr 11 mos)
Imagination Technologies
Hardware Engineer 2 (2 mos)
MosChip
ASIC Verification (2 yrs 6 mos)
Design and verification Engineer (1 yr)
Maven Silicon
Trainee (8 mos)
Education
VLSI-RN trainee at Maven silicon
btech at Sri Mittapalli College of Engineering, NH-5, Tummalapalem,PIN-522 233 (CC-U9)
Intermediate at Sri gayatri junior college
ssc at Sri Kondaveedu public school
