Praneeth Reddy — Product Manager

Graduate student from Portland State University with Masters in Electrical and Computer Engineering with specialization in Design Verification, and Computer Architecture. Actively Seeking Fulltime Opportunities in Design Verification Engineer roles to make valuable contributions to the company. I have 10-months of working experience as an IP Pre-Si Verification Intern at Intel Corporation, As an Intern I got exposure to areas like System Verilog, UVM, Linux. In my Internship I Contributed to the development of new verification methodology of Hard IP’s from the Full chip DV and defined the flow for the structured ASIC. I Worked on I/O subsystem - Maintaining the testbench, test cases and debugged test failures in standalone and thus improving the pass rate in regression and also reviewed the Verification Plan with the DV Lead and debugged the interface in Synopsys Verdi. As a part of my coursework in my Masters, I gained knowledge in Microprocessor System Design, System Verilog, Computer Architecture, Fundamentals of Pre-Silicon Validation.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in Design Verification methodologies.

Location: Portland, Oregon, United States

Experience: 2 yrs 10 mos