Rupinjeet Singh — Software Engineer

• Design verification (SoC DV, IP DV): Expertise in creation of verification plan, test bench development, generation of constrained random stimuli, scoreboard development, feature verification and debug, functional and code coverage analysis/closure. • Functional Safety (Fault Injection and FMEDA preparation) : Certified Functional Safety Engineer (ISO26262 by TUV-SUED) having expertise in flow development, workload development, strobe list definitions, fault extraction and injection, fault coverage analysis/closure, expert judgement. Experience in creation of FMEDAs. • Formal Verification: Expertise in doing SoC checks using formal techniques • Programming Languages: C/SV (UVM)/Specman-e/HDL (VHDL, Verilog) • Scripting languages: Perl, TCL • Tools: NCSIM, IEV, JG, Specman, XFS, vManager, vPlanner

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in Functional Safety and Design Verification.

Location: Bengaluru, Karnataka, India

Experience: 13 yrs 8 mos