Netra Balikai

Software Engineer

Bengaluru, Karnataka, India8 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Universal Verification Methodology (UVM)
  • Strong background in silicon design and verification
  • Proficient in multiple programming languages and verification tools
Stackforce AI infers this person is a Silicon Design Engineer with expertise in verification methodologies and programming.

Contact

LinkedIn

Skills

Core Skills

Universal Verification Methodology (uvm)Phy Veification

Other Skills

BSCANGLSNLPJoint Test Action Group (JTAG)DFTFunctional VerificationSystemVerilogC (Programming Language)PerlVerilog

Experience

8 yrs 9 mos
Total Experience
4 yrs 4 mos
Average Tenure
4 yrs 9 mos
Current Experience

Amd

2 roles

Member of Technical Staff

Jul 2025 – Present · 9 mos

Senior Silicon Design Engineer

Jul 2021 – Present · 4 yrs 9 mos

Universal Verification Methodology (UVM)BSCANPHY veification

Cerium systems

Senior verification Engineer

Jul 2017 – Jul 2021 · 4 yrs · Bengaluru, Karnataka, India

Education

B V B College of Engg. & Technology, HUBLI

Bachelor of Engineering - BE — Electrical and Electronics Engineering

Jan 2013 – Jan 2017

Stackforce found 100+ more professionals with Universal Verification Methodology (uvm) & Phy Veification

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