Sep 2018 – Aug 2020 · 1 yr 11 mos · Tamil Nadu

Sep 2016 – Jul 2018 · 1 yr 10 mos · Bengaluru Area, India

Jan 2014 – Jul 2016 · 2 yrs 6 mos · bangalore

• 1. Working on verifying complete memory subsystem including cache controller, ddr controller and other components as part of SoC with various masters driving the Subsystem.
• 2. Verifying smaller peripherals such as simple timers and other components which are part of SoC.

Mar 2013 – Dec 2013 · 9 mos · noida

• developed verification IP for latest upcoming packet based ARM protocol, CHI. Responsibilities include :
• 1. Coverage plan
• 2. Tests for hitting corner cases

Jan 2012 – Dec 2012 · 11 mos · bangalore

• Worked on Qualcomm's MSM chip. Role involved verifying DBI protocol and writing Glue logic using VHDL.

Jun 2010 – Dec 2011 · 1 yr 6 mos

• Worked on DDR3 PHY team which was used as part of APU

Aug 2009 – Jun 2010 · 10 mos

• Worked on functional verification and gate level simulations for DDR3 DFI compliant PHY.

Jul 2007 – Jun 2009 · 1 yr 11 mos

• Worked in verifying LPDDR/LPDDR2 memory controllers. Was also involved in updating synthesis scripts for legacy IPs and comparing the netlist and RTL using LEC.

Aug 2005 – Jun 2007 · 1 yr 10 mos

• Verified AMBA AXI related bridge with Freescale's CSB interface