Surya Javalkar — Software Engineer

I started my Career as FPGA Design Engineer for a Start up company for their FPGA Prototypes like Dual Band Communication Reciever which deals with Range, Azumith and Direction calculations for the Radar-Seeker laboratories. Worked on Avionics Mil 1553B protocol( both Busmonitor and Remote Terminal) RTL coding of the Prototype from the Initial Scratch, Verification on the Simulation tool and on Board level Testing Verification. Carried out Design and Verification of AXI to AHB conversion( with Master and Slave) for a processor core based on two VIVID core’s exploits parallelism (data,task & instruction) to enable a power & area efficient, fully programmable video processor which Supports Video applications ranging from encoding, decoding, pre/post processing with Testing on the Arm Versatile Platform Boards with ARM11 MPcore Processor (Core Tile), Vertex5 LX(Logic Tile) and Vertex 2 pro Devices. Worked on FPGA emulation for the Large Design with Four processors and Four DSP for a Multi Processor Networking Chip. Worked on Design of I2c high speed Protocol at 3.4Mbps and also for Mobile Integrated Solutions for developing Digital Design of Backup Battery Management for their SmartPhones. Specialties: Proficient in use of FPGA Design Tools: Xilinx ISE9.2i, Synplify Pro, Active HDL, ModelSim and ChipscopePro Analyzer, Alteras Quartus II , Time Quest timing analyzer, SignalTap II Logic Analyzer, Novas Debussy Tools - Springsoft - Verdi, Novas -nWave for Verification. Timing Analysis, Spyglass Linting tool. DFT rule checks for Synthesis. ClearCase tool.

Stackforce AI infers this person is a highly skilled FPGA Design Engineer with expertise in RTL design and verification.

Experience: 17 yrs 1 mo