Balram Mehetre — Director of Engineering

EXPERIENCE SUMMARY: • Over two decades of ASIC design experience with tech nodes from 18A, 3nm to 130nm, specializing in STA, PD, synthesis, digital design, verification, validation including team building and management. •Currently working as Senior Director Engineering at 7Rays Semiconductors India Pvt Ltd Bangalore •Worked as Principal Engineer PD at AMD Toronto, Canada, leading critical subsystems to achieve aggressive PPA targets for the latest Graphics IP. • Worked as Principal Engineer/Mgr at Qualcomm India with leading a team of 40+ engineers delivering high-performance DDR subsystem cores for Modem SoCs (from RTL to GDSII), as well as managing MSIP PD, RFA PD, and MSIP .lib characterization for various SoCs (MSM/MDM/Auto/IoT, C&N, and voice/music devices), and overseeing RF Analog layout teams. • Experience in Design/PD execution, engineering management and team building, mentoring, innovation and employee career growth. • RTL to GDSII project execution experience of 50+ multimillion gates complex ASIC designs (hierarchical, high frequency multi power domains) while managing teams of 40+ engineers across multiple sites and multiple functions. • Strong technical background covering majority aspects of ASIC front end and PD development. Good management interface and alignment at executive level to achieve aggressive business objectives. • Die size and schedule estimation along with design execution planning for complex ASIC’s. • Co-ordination with design, PD and package development teams for PD, PV, signoff timing constraints, signoff STA, packaging, FV/CLP and functional/timing ECO • Hands on experience on full chip Static timing analysis (STA), timing closure, IO interfaces like DDR, ONFI, post silicon debug, simultaneous multi voltage STA (SMVA), Synthesis (DCT-SPG), Physical design (ICC/Innovus), ECO flow, RTL, functional verification and FV/CLP of different multimillion gates ASIC designs. • Awarded with US patent 8959467 B2 - Structural rule analysis with tcl scripts in synthesis or STA tools and integrated circuit design tools • Technical lead for full chip Synthesis/STA and flow development for multimillion gates hierarchical ASIC designs • Micro architecture definition of different functional blocks. • Test environment design, test plans, full chip functional verification, block level functional verification and prototype testing of different ASICs / FPGAs. • Well aware of DFT, JTAG, SCAN and testing, DFT post silicon debug.

Stackforce AI infers this person is a Semiconductor professional with extensive experience in ASIC design and engineering management.

Location: Bengaluru, Karnataka, India

Experience: 25 yrs 10 mos