Shakti Malik

Software Engineer

Noida, Uttar Pradesh, India16 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

11 years of experience in EDA industry.
Expert in Gate/RTL Power Analysis.
Proficient in C/C++ on UNIX platforms.

Stackforce AI infers this person is a Software Architect in the EDA industry with a focus on power analysis and verification.

Contact

Skills

Core Skills

Power AnalysisSoftware DevelopmentFormal Verification

Other Skills

Average and Time-based power analysis enginesEngine netlist creationSimulation data processingPower modellingClock tree synthesisMixed-VT supportPower Gating supportPower profile generationRTL Power AnalysisC/C++LinuxCJAVAPerlSTL

About

# 11 year experience of software product development in EDA industry. # Expert in Gate/RTL Power Analysis. # Working in C/C++ on UNIX based Platform. Specialties: Programming Skills : C, C++, JAVA, Perl Expert in Data Structures and Algorithms, Shell Script Power Analysis, Machine Learning

Experience

16 yrs 9 mos

Total Experience

5 yrs 7 mos

Average Tenure

10 yrs 7 mos

Current Experience

Cadence design systems

4 roles

Software Architect

Promoted

Jul 2023 – Present · 2 yrs 10 mos

Senior Principal Software Engineer

Jul 2021 – Jul 2023 · 2 yrs

Principal Software Engineer

Jul 2018 – Jul 2021 · 3 yrs

Lead Software Engineer

Oct 2015 – Jul 2018 · 2 yrs 9 mos

Apache design solutions

2 roles

Sr. R & D Engineer

Promoted

Jan 2012 – Oct 2015 · 3 yrs 9 mos · Noida, Uttar Pradesh, India

Member of technical team responsible for RnD in Power-Artist Team. This includes development work in Average and Time-based power analysis engines.
Some of the key elements of my job are:
Engine netlist creation, Simulation data processing and propagation for RTL design, cell selection, Power modelling and power calculation, Clock tree synthesis for RTL design, Mixed-VT support for RTL design, Power Gating support using proprietary command and UPF/CPF, Power profile over time and waveform generation.

Power AnalysisAverage and Time-based power analysis enginesEngine netlist creationSimulation data processingPower modellingClock tree synthesis+4

Software Engineer

Dec 2010 – Dec 2011 · 1 yr · Noida, Uttar Pradesh, India

Member of Power-Artist team. Worked in RTL Power Analysis.

RTL Power AnalysisPower Analysis

Atrenta

Software Engineer

Jul 2009 – Dec 2010 · 1 yr 5 mos

Member of Formal Technology Group & SpyGlass-CDC Group. Some key elements of my job were:
Formal Verification flow setup, design & problem modelling for the purpose of verification of properties on formal tools like SAT, BDD. Engineering, development (C/C++ on Linux platform), testing & debugging related activities with SpyGlass–CDC using SpyGlass Platform.

Formal VerificationC/C++Linux