Ajesh K Madhavan

Software Engineer

Bengaluru, Karnataka, India17 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Physical Design and Static Timing Analysis.
Proven experience in Low Power and High Frequency Designs.
Strong background in advanced technology nodes.

Stackforce AI infers this person is a VLSI Design expert with a focus on Physical Design and Static Timing Analysis.

Contact

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

SynthesisLow Power DesignHigh Frequency DesignsPhysical VerificationEDATiming ClosureFloorplanningPrimetimeSoCASICFunctional VerificationFormal VerificationClock Tree SynthesisPower AnalysisDRC

About

Physical Design Lead at Intel Corporation Specialties: PNR, STA, Synthesis and signoff in Low Power and High Frequency Designs in various advanced technology nodes.

Experience

17 yrs 6 mos

Total Experience

5 yrs 10 mos

Average Tenure

11 yrs 8 mos

Current Experience

Intel corporation

2 roles

Senior Physical Design Engineer

Jan 2021 – Present · 5 yrs 3 mos

Physical DesignStatic Timing AnalysisSynthesisLow Power DesignHigh Frequency Designs

Physical Design Engineer

Aug 2014 – Present · 11 yrs 8 mos

Physical DesignStatic Timing AnalysisSynthesisLow Power DesignHigh Frequency Designs

Synapse design automation inc.

Senior Physical Design Engineer

Aug 2011 – Jul 2014 · 2 yrs 11 mos · Bangalore

Synthesis, Physical Design, Physical Verification, Static Timing Analysis

SynthesisPhysical DesignPhysical VerificationStatic Timing Analysis

Wipro technologies

Physical Design Engineer

Aug 2008 – Jul 2011 · 2 yrs 11 mos · Cochin, India

Synthesis, STA, Physical Design, Physical Verification

SynthesisStatic Timing AnalysisPhysical DesignPhysical Verification

Education

Vellore Institute of Technology

M.Tech — VLSI Design

Jan 2006 – Jan 2008

Cochin University of Science and Technology

B-TECH — ECE

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