punit kishore

Associate Partner

Bengaluru, Karnataka, India21 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in DFT for high-speed IO testing.
Led global DFT initiatives at NXP Semiconductors.
Proven track record in automotive DFT strategies.

Stackforce AI infers this person is a Semiconductor and Automotive DFT expert with extensive leadership experience.

Contact

Skills

Core Skills

DftSoc

Other Skills

ATPGBISTAutomotive DFTHSIO based structural testingHSIOSCANHigh speed IOCharacterizationJTAGMEMORYTetramaxFastscanRTL designStatic Timing AnalysisASIC

About

Solid background in dfx planning and implementation for wide range of SOCs (gpu, tegra, mcp, omap, icera-modem). Expert in defining strategy for test and characterization of high speed IO. Organizational development through engineering management is core strength.

Experience

21 yrs 7 mos

Total Experience

4 yrs 3 mos

Average Tenure

4 yrs 5 mos

Current Experience

Nxp semiconductors

Senior Director DFT

Dec 2021 – Present · 4 yrs 5 mos

Leading India DFT Team (ACE, NXP) and also playing global DFT Architect for NXP.

DFTATPGBISTSoC

Qualcomm

2 roles

Design Manager

Mar 2021 – Dec 2021 · 9 mos

worked as design manager for MSM and XR socs.

principal/Mgr

Aug 2017 – Mar 2021 · 3 yrs 7 mos

Technologist for DFT team. Drove multiple key initiatives : HSIO based structural testing, Automotive DFT, Concurrent SCAN solution.

DFTAutomotive DFTHSIO based structural testing

Intel corporation

Senior Engineering Manager

Apr 2016 – Jul 2017 · 1 yr 3 mos · Bangalore Urban, Karnataka, India

Led TFM team in DTEG, Bangalore.

Nvidia

3 roles

Cricket team captain

Jun 2011 – Jan 2016 · 4 yrs 7 mos

You can follow my cricket team activity at www.facebook.com/NvidiaCricket
While playing cricket learned lot about team-building and leadership. Good part is, this learning is unique :) but not acquired in a class-room.

Engineering hardware manager (DFT)

Promoted

Dec 2010 – Apr 2016 · 5 yrs 4 mos

Manager of high speed IO test and characterization group.

High speed IOCharacterizationDFT

Senior DFT Engineer

Sep 2005 – Dec 2010 · 5 yrs 3 mos

Major responsibilty :
1. DFT design/implementation/verification for SCAN, MEMORY, IO, JTAG .
2. Silicon bringup on ATE

Texas instruments

Wireless Design Engineer

Jan 2004 – Jan 2005 · 1 yr

Worked on designing a L2 cache controller for ARM11 core. This was for OMAP generation SoC. Worked on implementing a PPAS driven DFT structure. PPAS stands for :
P[power]
P[performance]
A[Area]
S[Schedule]

DFTJTAGMEMORY