Deepak Garg — CEO
A Blend of StrongTechnical Competencies with Good Business Sense (MBA in International business from IIFT Delhi) and understanding of the Semiconductor Industry (BTech from NIT Warangal) with 24+ Years of Experience of Full ASIC Cycle. Having & Nurturing Portfolio of Constraints & Power Team & Signoff STA & Physical Design as proven Leaders. Good FE/DV fundamentals help me to drive BU with Correct by Construction Approach aiming Zero defect (FTSS) silicon with Competitive PPA. Leading & Managing Physical Design & Signoff with Developing with various check and Conceptualizing Strategy for a. PPA optimization. b. Execution Efficiency with Correct by Construction Approach. c. Quality (Zero re-work) due to quality misses in intermediate milestone. d. Zero Post Silicon Bugs in Signoff e. Created A Captive teams from ground zero to operational excellence. Technical Expertise : (07nm,10nm,12nm,14nm,28nm,40nm,65nm implementation) Leading an Implementation team for RTL to SIGNOFF. Seasoned in SOC Planning & Architectural requirements leading Execution plan via milestones. Expert in Driving Clock Strategy for SOC & Budget Techniques. Expert in Driving Power Requirements and strategy for SOC/SS. Expert in SoC Signoff Static Timing Analysis, Clock Management, DFX Concept, Physical Design Implementation & Mitigation Plan Formulating STA Strategies and Risk Management. Good Cross-functional Coordination and Mentoring. Managed SoC integration, Subsystem developement Managed Silicon Vadilation support. Had hands on IP and SOC verification, Emulation platform using Axis n specman. Extensively worked on high definition Set Top Box . 28+ APSOC Tapped out with Good Success record.
Stackforce AI infers this person is a semiconductor industry expert with extensive experience in ASIC design and physical design management.
Location: Bengaluru, Karnataka, India
Experience: 24 yrs 4 mos
Skills
- Asic Design & Implementation
- Soc Signoff Ta
- Soc Integration
Career Highlights
- 24+ years of experience in full ASIC cycle.
- Expert in SOC Signoff and Static Timing Analysis.
- Proven track record in building high-performance teams.
Work Experience
L&T Semiconductor Technologies
Department Head: Physical Design & Signoff (1 yr 6 mos)
Intel Corporation
Sr Engineering Manager (6 yrs 5 mos)
Qualcomm
Senior Staff Engineer (2 yrs 4 mos)
ST MicroElectronics Pvt Ltd
Senior Staff Engineer/Manager (11 yrs 7 mos)
Wipro Technologies
VLSI Design Engineer (2 yrs 1 mo)
Lecturer: (Adhoc Faculty of NIT Jaipur and Gyan Vihar University
Lecturer (5 mos)
Education
EPGDIB at Indian Institute of Foreign Trade
Bachelor’s Degree at National Institute of Technology Warangal
