Apr 2023 – May 2025 · 2 yrs 1 mo

• SoC Architecture, PPA trade-off analysis, coherent interconnect, cache hierarchy, topology design, performance modeling (Gem5), correlation

Jun 2022 – Apr 2023 · 10 mos

• C++ performance modeling, correlation, performance verification for coherent interconnect and system cache (NCore)

Sep 2019 – Jun 2022 · 2 yrs 9 mos

• Worked with customers to help them architect, design, implement and successfully tape-out SoCs with Arteris interconnect solutions
• NoC architecture, mesh topology, virtual channels, deadlock detection, customer focus

May 2017 – Sep 2019 · 2 yrs 4 mos · Greater San Diego Area

• NoC design for mobile SoCs, floorplan-partitioned interconnect topology, chip address map, synthesis/CDC/Lint flows, UVM verification, perf analysis

Feb 2015 – May 2017 · 2 yrs 3 mos · Greater San Diego Area

Jun 2014 – Sep 2014 · 3 mos · Greater San Diego Area

• Post-Si validation, DVFS testing, scalable configuration sequence coding

Jul 2011 – Jun 2013 · 1 yr 11 mos · Bengaluru Area, India

• SoC DV, Waveform debug, Tool development, Scripting, Perl