Vrushabh Damle — Software Engineer
As a Design Engineer I at Cadence, I specialize in analog layout design using Cadence Virtuoso. I began my journey with a year-long internship at Cadence, which transitioned into a full-time role in August 2024. My work primarily revolves around memory IP layout, where I’ve developed a strong foundation in custom design practices. I’ve worked with advanced process nodes including Samsung’s 2nm MBCFET, 4nm FinFET, and TSMC’s 3nm FinFET technologies. I’m proficient in running and debugging DRC, LVS, and EM-IR checks, and have hands-on experience optimizing layouts to meet tight design and reliability constraints at the bleeding edge of semiconductor innovation.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in analog layout and integrated circuit design.
Location: Pune, Maharashtra, India
Experience: 1 yr 9 mos
Skills
- Analog Integrated Circuit Design
- Analog Layout
Career Highlights
- Specializes in analog layout design at Cadence.
- Experience with cutting-edge semiconductor technologies.
- Proficient in DRC, LVS, and EM-IR checks.
Work Experience
Cadence Design Systems
Design Engineer I (1 yr 9 mos)
Intern Design Engineer (1 yr 1 mo)
Cereble
Embedded Design Engineering Intern (6 mos)
Verzeo
Internet of Things Intern (2 mos)
Education
Bachelor of Engineering - BE at Pune Institute of Computer Technology
