Apr 2019 – Jul 2022 · 3 yrs 3 mos · Santa Clara

• I am thankful to Apple for providing opportunity for me to serve these 3.5 years.

Feb 2018 – Apr 2019 · 1 yr 2 mos · Santa Clara

• Senior Layout Engineer in R & D department.

Jan 2017 – Jan 2018 · 1 yr · Santa Clara, United States of America

Nov 2015 – Jan 2016 · 2 mos

• Helper for TII project in doing sub blocks of 4T4R project. Did layout for sub-blocks and helped top level team to do the clock buffering. Executed project in 40nm.

Jul 2015 – Oct 2015 · 3 mos

• Worked on layout for RF chip. Blocks include BBLNA, BBRx, ADC, GMFilter, Transmitter, Upconverter/Mixer, LDO.
• This is the new customer and hence challenge was to build good relationship with them and give best service to them to gain their confidence.

Jul 2005 – Mar 2011 · 5 yrs 8 mos

• First two years I worked in I/O group as an individual contributor then in ANALOG LAYOUT group as an experienced member for 2.5 years and then I was leading analog layout group for 1 year. I did many of high speed transceiver blocks during this time like HDMI Transmitter, USB2 and USB3 Transmitter, Camera Receiver, MPHY Transmitter, and then Integration of Test chip which includes PAD ring and IPs.

Jun 2005 – Jun 2015 · 10 yrs

• Working on Mixed Signal Analog layouts for one of our customer by leading a team of 7 members. Worked on different types of DAC. Worked on FinFET technology.