Silva Khachatryan

Product Manager

Yerevan, Armenia15 yrs 2 mos experience
Highly Stable

Key Highlights

  • Expert in managing multi-site analog layout teams.
  • Proficient in VLSI and Physical Verification.
  • Extensive experience in layout design for high-speed circuits.
Stackforce AI infers this person is a Semiconductor Design Expert with strong leadership in VLSI layout management.

Contact

Skills

Core Skills

VlsiPhysical VerificationAnalog Circuit Design

Other Skills

Custom DesignerPhysical/Formal VerificationEmbedded SystemsICVCalibreLinuxAnalogSRAMDebuggingMixed SignalCompilersHERCULESSchematic/Layout DesignVerilogSemiconductor design / Manufacturing

About

[2023/02-to present] “Synopsys Armenia”. "Yerevan, Armenia" “R&D Layout Design manager” SerDes layout design Main duties and responsibilities • Managing and leading of multiple projects of DPHY/CDPHY/CPHY products (extremely low nodes) • Creation and investigation for new architectures of the product. Layout design reviews, etc. • Leading an experienced multi-site analog layout team • Working closely with various teams from different sites (design team, CAD team, release team, etc.) *Layout Design of High Density, High Speed, RF, Embedded SRAM Memory Systems * Layout Design of Logic cell Libraries * Layout design of Analog and Mixed Signal Circuits (DAC, ADC, PLL, OpAmp, etc) * QA and Verification flows for Memory/logic/analog Layouts * Physical Verification and Debug

Experience

15 yrs 2 mos
Total Experience
15 yrs 2 mos
Average Tenure
15 yrs 2 mos
Current Experience

Synopsys inc

7 roles

A&MS R&D Layout Manager

Promoted

Dec 2023Present · 2 yrs 4 mos

VLSIPhysical VerificationCustom DesignerPhysical/Formal VerificationEmbedded SystemsICV+7

Supervisor

Feb 2023Dec 2023 · 10 mos

Team Lead Manager

Promoted

Apr 2022Feb 2023 · 10 mos

R&D Engineer Sr

Nov 2021Apr 2022 · 5 mos

R&D Engineer 2

Promoted

May 2015Dec 2021 · 6 yrs 7 mos

R&D Engineer

May 2011Apr 2015 · 3 yrs 11 mos

Intern

Dec 2010Apr 2011 · 4 mos

  • ICV/HERCULES/CALIBRE deck writing.
  • Schematic/Layout Design of SRAM/ROM memory systems.
  • Physical and formal verification.
  • Digital standard cell library design
  • SAED library release.(90nm)

Education

Synopsys Armenia Educational Department (SEUA)

MS

Jan 2010Jan 2012

Synopsys Armenia Educational Department (SEUA)

BS

Jan 2008Jan 2010

N114 named after Khachik Dashtenc

Jan 1996Jan 2006

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