Ketan Shet

Software Engineer

Bengaluru, Karnataka, India10 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Extensive experience in ASIC design and verification.
  • Proficient in multiple EDA tools and programming languages.
  • Strong background in RTL design and physical design methodologies.
Stackforce AI infers this person is a VLSI design engineer with expertise in ASIC development and verification.

Contact

LinkedIn

Skills

Other Skills

VerilogApplication-Specific Integrated Circuits (ASIC)TestabilityPerlPhysical DesignTCLSystem VerilogDFTRTL DesignRTL CodingCadence VirtuosoAltera QuartusModelSimTessentSynopsys tools

Experience

10 yrs 7 mos
Total Experience
3 yrs 6 mos
Average Tenure
5 yrs 8 mos
Current Experience

Samsung semiconductor

3 roles

Senior Staff Engineer

Promoted

Mar 2024 – Present · 2 yrs 2 mos

Staff Engineer

Promoted

Feb 2022 – Feb 2024 · 2 yrs

Associate Staff Engineer

Aug 2020 – Feb 2022 · 1 yr 6 mos

Mediatek

3 roles

Senior Engineer

Promoted

Jun 2019 – Aug 2020 · 1 yr 2 mos

Engineer

Jul 2018 – Jun 2019 · 11 mos

Intern

Jul 2017 – Jun 2018 · 11 mos

Cognizant technology solutions

Programmer Analyst

Aug 2014 – Jul 2016 · 1 yr 11 mos · Pune

Education

Vellore Institute of Technology

Master of Technology (M.Tech.) — VLSI

Jan 2016 – Jan 2018

Dr. Babasaheb Ambedkar Technological University, Lonere

Jan 2010 – Jan 2014

Stackforce found 100+ more professionals with Verilog & Application-Specific Integrated Circuits (ASIC)

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