J

jeevan gr

Software Engineer

Bengaluru, Karnataka, India19 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in ASIC and Functional Verification.
  • Strong background in VLSI design and debugging.
  • Proven track record in leading engineering projects.
Stackforce AI infers this person is a VLSI and ASIC design expert with a focus on functional verification.

Contact

LinkedIn

Skills

Core Skills

AsicFunctional Verification

Other Skills

Formal VerificationApplication-Specific Integrated Circuits (ASIC)DebuggingCRTL designVLSIVHDLVerilogSoCRTOS

Experience

19 yrs 3 mos
Total Experience
3 yrs 10 mos
Average Tenure
6 yrs 5 mos
Current Experience

Qualcomm

Staff Engineer

Nov 2019 – Present · 6 yrs 5 mos · Bengaluru, Karnataka, India

Formal VerificationApplication-Specific Integrated Circuits (ASIC)ASICDebuggingCFunctional Verification+6

Intel corporation

Component Design Engineer

May 2016 – Nov 2019 · 3 yrs 6 mos · Bengaluru Area, India

Cadence design systems

Lead Application Engineer

Mar 2012 – May 2016 · 4 yrs 2 mos · Bengaluru Area, India

Nokia india

Design Engineer

Jan 2008 – Mar 2012 · 4 yrs 2 mos

Reliance retail

Management trainee

Jan 2005 – Jan 2006 · 1 yr

Education

Visvesvaraya Technological University

M.Tech — VLSI

Jan 2006 – Jan 2008

viswa manava college

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