Basheer Ahamed Batcha H — Software Engineer
I am an ECE Engineer having a strong interest in technology and fond of solving complex problems in a most simple way.Currently, working as an ASIC design verification engineer in various projects that involves developing UVM testbench, creating testplan, writing testcases, functionality checking and RAL model implementation . • Verification Language: System Verilog,Assembly Language. • Methodology: UVM. • Protocols used: APB,AHB,AXI, DDR3, MIPS, UART and PCIe. • Simulator tools: Aldec Riviera PRO, Cadence NC-Sim, Synopsys Verdi.
Stackforce AI infers this person is a highly skilled ASIC design verification engineer specializing in semiconductor technology.
Location: Bengaluru, Karnataka, India
Experience: 7 yrs
Skills
- Universal Verification Methodology (uvm)
Career Highlights
- Expert in ASIC design verification with UVM methodology.
- Proficient in System Verilog and various communication protocols.
- Strong problem-solving skills in complex technical challenges.
Work Experience
Microsoft
Senior Design Verification Engineer (1 yr 1 mo)
Design Verification Engineer - II (1 yr 5 mos)
MediaTek
Senior Verification Engineer (2 yrs 1 mo)
HCL Technologies
ASIC Verification Engineer (11 mos)
Green Semiconductors Pvt ltd
Design Verification Engineer (1 yr 6 mos)
QSoCs Technologies
Design And Verification Engineer Trainee (6 mos)
Education
Bachelor of Engineering (BE) at Mepco Schlenk Engineering College
HSC at St.Xavier's Hr.Sec.School, Palayamkottai-627011
SSLC at M.N.Abdur Rahman Hr.Sec School , Palayamkottai -627011
