Jan 2024 – Jul 2024 · 6 mos · Hyderabad · On-site

• Responsible for Silicon Solutions at Smart SoC Solutions, overseeing the development and expansion of a highly skilled team and Business.

Jul 2017 – Aug 2023 · 6 yrs 1 mo · Hyderabad, India

• Throughout my tenure as a Director – Silicon Design Engineering, my responsibility has been to manage Graphics Core verification, design, development, and deployment of Audio & Video Ips to AMD roadmap SOC Programs.
• Further, my emphasis was on building a brand-new team of 125+ talented engineers and knowledge managers from diverse backgrounds across multiple sites for Graphics Core verification. Formed and expanded a Video IP team in India to 45+ within one year; initially started with deployment of Video IP to all Client SOCs and eventually developed all the skills within the team – Micro architecture, RTL design and integration, Design Verification, Synthesis, timing closure, and post-silicon debug.
• Meanwhile, I lead multiple functions PPA, functional verification, performance verification, hardware emulation, post-silicon bring up and validation. Spearhead project planning, resource management, and performance management of organization. Drive the design of major features (EFC, SMP BE, JEG, UMS, etc.) for multiple versions of Video IP in collaboration with the global team and delivery of high high-quality IP to Client, dGPU, Data Center and customer SOCs.
• Moreover, I direct the network of knowledge (A community platform for knowledge sharing) and develop methodologies to convert tacit knowledge to explicit knowledge.
• In addition, roles required me to steer Innovation Charter for Multi-media and RTG teams.
• As a People Leader, I am recognized for building and leading high-performing, strong, large, world-class engineering teams globally (150+) including engineers (direct reports) at different grade levels Senior Managers, PMTSs, Managers and SMTSs, that consistently delivered high quality products at an aggressive cadence. Influencing individuals, organizations, technologies and industry with proven leadership and ability to work collaboratively across teams, organizations, and management levels.

Mar 2010 – Jul 2017 · 7 yrs 4 mos · Hyderabad, India

• While working as a Senior Manager, my accountabilities were to build a brand-new team to develop Audio IP in Hyderabad, India. Expanded the team to 40+ engineers within 8 months.
• Successfully spearheaded the HW and FW teams; designed a bug free Audio IP complete solution and delivered to complex SOC (Game console box – PS4). Championed the design, verification, and validation teams throughout the execution until a successful Silicon bring up for multiple generations of Audio IP; coordinated SW development for the Audio IP and aligned them towards productization schedule.
• Besides, I led Video IP deployment team (20 engineers) and delivered high quality IP to multiple SOCs. Planned, directed and executed the design & development of Audio and Video IP. Delivered multiple versions of Audio IP with high quality to different product lines. Initiated Internship program in AMD at site level to tap top talent from universities at master’s level.

Jan 2007 – Feb 2010 · 3 yrs 1 mo · Hyderabad, India

• At Nvidia Graphics, I constructed a System Engineering team (30 engineers) and established USB, FPGA, and Silicon validation labs in Hyderabad site. Managed global teams for silicon validation of multiple SOCs.
• Furthermore, my focus was on planning, tracking, and execution of silicon validation effort for multiple SOCs. I was involved in performance management, career guidance to team members, and budget tracking.
• Throughout, I led FPGA board design team and FPGA Validation; successfully led continuous 72 hour bring up of Tegra-1 silicon in Santa Clara, USA. Established USB, Silicon validation and FPGA labs in Hyderabad site, India.

May 2005 – Dec 2006 · 1 yr 7 mos · Hyderarabad

• Managed a team of 15 members. Responsible for 3rd party IP evaluation and integration in SOC. Led the verification & post silicon bring up activities of Portal player’s 5020LP chip. Built a brand new system engineering team of 10 members

Oct 2004 – Apr 2005 · 6 mos

• Design Lead for customer project and FPGA validation

May 2001 – Sep 2004 · 3 yrs 4 mos · Hyderabad

• Led a team of 20 members, owned major portion of the design hands. Detailed architecture, micro-architecture, code and verification reviews helped to deliver bug free design of USB2Ethernet controller. First time working silicon went into production and shipped millions of units
• Accountable to drive the project from specification to silicon.
• Coordinated very closely with Faraday Technology Corporation to integrate their USB2.0 and 10/100 Ethernet Phys to our design.
• Responsible to port the design on FPGA and validation

Apr 2000 – May 2001 · 1 yr 1 mo · Hyderabad

• Front end RTL design and verification. Involved in the USB 2.0/1.1 controller Design and Verification

Jan 1992 – Dec 2000 · 8 yrs 11 mos · Hyderabad, India

• Taught at Graduate and Undergraduate Level, guiding academic projects in VLSI. Taught Digital Electronics, Computer Architecture, Microprocessors and VLSI subject at Graduate & Undergraduate level. Guided many academic projects with Verilog HDL

Jan 1989 – Dec 1991 · 2 yrs 11 mos · Hyderabad, India

• Taught at Undergraduate Level, guiding academic projects in VLSI and Digital Electronics.

Aug 1988 – Jan 1989 · 5 mos · Hyderabad, India

• Design and Development of Microprocessor based Energy meters.