Dec 2023 – Mar 2025 · 1 yr 3 mos

• Working on SoC functional validation of Intel Foundry 18a test chip and customer designs on Intel 3 & intel 18a process node.
• Leading PCIe post silicon functional validation and power-on activities. Working with key stakeholders across Design, Architects, Pre-Si verification, Software and firmware teams for successfully bringing up PCIe features.
• Developed validation strategy (this includes scoping, tools, finalizing pre/post silicon features to be tested), wrote test plans & test scripts and executed of the same in pre & post-silicon environment.
• Developed C (BareMetal) & Python based test scripts from scratch for ZeBu based emulation platforms.
• Ramped up expertise in UCIe, IO virtualization including creating validation strategies and test plans .
• Mentored and onboarded recent college graduates and interns, fostering their growth and integration into the team.
• Contributed to recruitment by shortlisting resumes and conducting early-stage interviews for junior engineering roles.

Dec 2021 – Nov 2023 · 1 yr 11 mos

• Leading PCIe & Telemetry post silicon functional validation for Intel Data Center Max GPUs. This is continuation of all activities I have done in previous role.
• Have done platform level validation for OAM (600 Watt) & PCIe (300 Watt) form factor data center GPUs focusing on PCIe & telemetry features.
• Involved in setting up customer (Dell, Lenovo, Supermicro, Wistron) server blade like server platforms in India site lab for platform validation.
• Developed and executed test plans and test scenarios that is made to stress the whole server blade involving multiple CPUs & GPUs.
• Exposure to Intel server gpu platform tools SoCwatch, PTUMon, PTAT, XPUTool, sysman.
• Exposure to workloads (HPL, LAMMPS, MPI-HACC, CLPeak, Dgemm) that are designed stress the entire server platform topology and expose corner scenarios.
• Debugged scenarios where incorrect power, incorrect temp was reported during workload runs

Jan 2020 – Dec 2021 · 1 yr 11 mos

• Contributed to pre and post-silicon validation and power-on activities for data center GPUs & accelerators (aka Intel Data Center Max GPU).
• Gained expertise in executing tests on transactor-based ZeBu emulation models, FPGA models, speed adapter-based in-circuit emulators (ICE), and silicon.
• Designed and implemented PCIe test plans, including automated Python-based test scripts for PCIe Gen3/4/5 link bring-up, link stability, ASPM L1, PML1, L2/L3 low-power scenarios, hot reset, link disable, FLR, error logging, and LTSSM FSM logging.
• Facilitated PCIe compliance certification testing across pre-silicon and post-silicon environments.
• Diagnosed and resolved complex PCIe and telemetry issues, such as speed drops, width drops, link instability during system resets, enumeration challenges, compliance violations, kernel panics, and incorrect telemetry/crash log data collection.
• Led cross-site task forces, collaborating with designers, architects, and verification engineers to accelerate power-on debugging and resolve complex issues efficiently.

Jul 2018 – Jul 2019 · 1 yr · Bengaluru, Karnataka, India · On-site

• Worked on Elkhart Lake SoC as an intern in the post silicon validation team.
• Gained expertise in ARM Cortex-M class architecture, including SPI, I2C, and GPIO.
• Developed test plans and verification scripts, performed validation on SPI, GPIO, error injection-detection and logging, ensuring thorough verification on FPGA as part of power-on readiness activities.
• Performed hands-on lab work to bring up and set up STRATIX-10 FPGA boards, utilizing JTAG-based hardware debuggers, ARM ULink Pro, and software IDEs to streamline debugging and development processes.