Shofiqul Islam

Software Engineer

Hyderabad, Telangana, India22 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in front-end ASIC design and verification.
Proven track record in VLSI design and low power implementation.
Extensive experience in processor architecture and digital signal processing.

Stackforce AI infers this person is a VLSI design expert with a focus on ASIC and processor architecture.

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Skills

Core Skills

Front-end Asic Design FlowVlsi Design

Other Skills

VerilogSoCVLSIStatic Timing AnalysisTCLASICCC++PerlTcl/TkShelleQELMATLABDigital design

About

After graduation from NIT Durgapur in 2003, I have been working on ASIC design flow. I have worked on several SoCs which have been successfully taped out. I want to work on VLSI signal processing design and verification, low power implementation and processor architecture. Specialties: 1] Front-end ASIC design flow - Micro-architecture design, RTL coding, verification, synthesis, STA 2] VLSI design: languages - Verilog, VHDL, Cadence and Synopsys EDA tools 3] Programming languages: C, C++, Perl, Tcl/Tk, Shell, e, QEL 4] Algorithm Developmet: MATLAB 5] Digital design 6] RISC processor architecture 7] Digital signal processing

Experience

22 yrs 8 mos

Total Experience

7 yrs 6 mos

Average Tenure

17 yrs 7 mos

Current Experience

Broadcom

Principal Engineer

Oct 2008 – Present · 17 yrs 7 mos · Hyderabad Area, India

1] Implementation of channel equalizer algorithm, verification, integration too teletext decoder module. Synthesis and timing closure
2] Bridge design for AMBA AXI protocol to DDR2 memory controller interface, verification
3] MIPS M4K processor subsystem design with SRAM and read/write interface and interrupts. Formal verification of the design
4] Audio sub system integration to SoC, timing closure for I2S, SPDIF interfaces
5] Design, verification, synthesis, STA of various peripheral IPs like SPI, NAND, Timers, WDTimers, Interrupt Controllers, Boot devices etc for various SoCs from last 3+ years.

VerilogSoCVLSIStatic Timing AnalysisTCLASIC+2

Amd

Senior Design Engineer

Feb 2007 – Oct 2008 · 1 yr 8 mos · Hyderabad Area, India

1] Work on MIPS processor - integration to SoC, verification, synthesis
2] Emulation using Cadence Palladium hardware
3] Low power simulation using CPF
4] Interface timing analysis

VLSI design

Anurag, drdo

Scientist "C"

Aug 2003 – Jan 2007 · 3 yrs 5 mos · Hyderabad Area, India

1] Design and implementation of 32-bit high speed RISC processor
Design new pipeline architecture
Design instruction decoder, dependency resolver, register file, ALU
Design on-chip interrupt controller
Verilog coding, verification and synthesis
2] Design and verification of 2 forward error correction algorithms, integration to SoC

VLSI design