Aug 2019 – Present · 6 yrs 7 mos · Bangalore

• Performed power analysis, optimization, and recovery flow development, along with comprehensive power modeling.
• Collaborated effectively with cross-functional teams encompassing Design, Design Verification, Synthesis, Physical Design, Power Delivery Network (PDN), System PDN, Thermal, and Post-Silicon engineering to ensure successful CPU power recovery and sign-off.
• Streamlined workflows and implemented innovative methodologies through scripting and process improvements.
• Contributed to the successful tape-out of eight integrated circuits across multiple technology nodes (11nm, 8nm, 7nm, and 4nm).
• Developed expertise in low-power design and CPU low-power modes, providing proactive recommendations to post-silicon teams based on pre-silicon analysis.
• Independently executed various tasks and troubleshooting activities related to power analysis.
• Developed power models to enable comprehensive power analysis across process, voltage, and temperature (PVT) conditions and operational modes, facilitating post-silicon correlation.

Jan 2019 – Jun 2019 · 5 mos · Greater Bengaluru Area

• Responsible for environment bring up to analyse power consumption for SOC design using Ansys Power Artist.
• Analysis of power critical IPs to minimise average power consumption across SOC.
• Application of low power techniques and other possible architectural and design changes at RTL level to optimise power.