SRINIVASU Y — Consultant

 Successfully taped out 30+ projects using 28nm ,40nm ,55nm ,65nm ,90nm ,110nm TSMC G+/LP process technologies..  Have directly handled multiple full chips and multiple blocks in different projects and supported full chip activities in projects.  Strong exposure to a large spectrum of backend design activities encompassing Logic synthesis, Bump Plan, IO ring creation, Top level Floorplaning , partition, pin & bus plan ,P&R, Power analysis, Signal integrity analysis, Timing Analysis and Physical verification.  Good knowledge in low power flow concepts and implementations methodology.  Good knowledge on sh , perl , python and Tcl/TK scripting. Ability to set design flows.  Hands on experience in handling Place & Route and STA in tools/Platforms like SOC Encounter, NanoRoute, PKS, IC Compiler, Star-RCXT, PrimeTime , Calibre, Sierra Pinnacle.  A Dedicated and confident player with inherent focus on quality and relationship building.  Technically proficient with proven ability to manage, communicate effectively and deliver on-time technical solutions to maximize business value.

Stackforce AI infers this person is a VLSI Design Engineer with extensive experience in backend design and physical verification.

Location: Bengaluru, Karnataka, India

Experience: 21 yrs 5 mos