SHILPA PUSHPAN — Software Engineer

Electronics and Communication Engineering graduate doing training in Physical Designing. CORE COMPETENCIES : * Good Knowledge in ASIC Flow (RTL to Tape out) ,Physical Design implantation * Working knowledge of Linux, VI editor and Programming in C, Perl, Tcl, Verilog * Static Timing Analysis, Floorplan, Placement, CTS, Routing,Physical verification, Synthesis, DFM, DRC, LVS, Parasitic Extraction, Schematic, Layout and Spice Simulation. * Familiar with 180nm technology * Basic knowledge in Reliability issues like EM, IR drop, Congestion and Floating Pin errors * Ability to analyze timing paths, timing reports, fix setup and hold in Flip Flop based and Latch based Designs in STA * An understanding of top view and cross sectional view of CMOS, MOSFET and BJT. Tools: Placement and Routing : Synopsys IC Compiler Synthesis : Synopsys Design Compiler STA : Synopsys Prime Time Verilog : Questasim

Stackforce AI infers this person is a VLSI Design Engineer with expertise in physical design and ASIC implementation.

Location: Bengaluru, Karnataka, India

Experience: 8 yrs 11 mos