Siddheshwar A

Software Engineer

Bengaluru, Karnataka, India15 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Physical Design and SoC implementation.
Led multiple projects in test chip and macro design.
Recipient of Outstanding Performer award at SmartPlay.

Stackforce AI infers this person is a Physical Design Engineer specializing in SoC implementations within the semiconductor industry.

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Skills

Core Skills

Physical DesignSoc

Other Skills

FloorplaningTiming closureNetlist to GDSTest chip implementationMacro implementationRTL to GDSBlock level Physical DesignClock Tree SynthesisStatic Timing AnalysisCompilersPhysical VerificationVirtuosoVerilogEDASignal Integrity

About

Technical Lead Physical Design/ Implementation Technical Expertise in Test chip and Macro implementation and signoff • Floorplaning of SOC and Block level (Placement of Micros, Voltage island creation, Power planning) • Placement • CTS(Clock Tree Synthesis) • Route • Timing closure • Physical verification • Power analysis and optimize • Convenient in handling Heard macro with multimillion instance and Hierarchical design. • Experience in working on various tools. • Test Chip implementation and signoff o Creation of IO ring o IO PAD placement (Signal PAD and PG PAD placement as per guidelines) o PG Ring creation o BUMP placement as per implementation guidelines o BUMP assignment o RDL routing o Entire PnR and all sign off activities

Experience

15 yrs 3 mos

Total Experience

2 yrs 11 mos

Average Tenure

4 yrs 6 mos

Current Experience

Qualcomm

Staff Engineer ,SOC Physical Design,Floorplan

Nov 2021 – Present · 4 yrs 6 mos · Bengaluru, Karnataka, India · Hybrid

Physical DesignSoCFloorplaningTiming closure

Samsung

PD Project Lead consultant

May 2018 – May 2022 · 4 yrs · Bangalore

Netlist to GDS of Test chip and Macros,
Implementation Led two projects and currently Leading three projects in parallel.

Netlist to GDSTest chip implementationMacro implementationPhysical DesignSoC

Mediatek

Senior Consultant

Nov 2017 – Apr 2018 · 5 mos · Bangalore

Netlist to GDS

Netlist to GDSPhysical Design

Qualcomm

Engineer 3

Feb 2016 – Oct 2017 · 1 yr 8 mos · Bangalore

Physical design RTL to GDS

Physical designRTL to GDSPhysical Design

Mindlance technologies

Technical Lead

Jan 2016 – Apr 2018 · 2 yrs 3 mos · Bangalore

Netlist to GDS

Netlist to GDSPhysical Design

Pmc-sierra

Senior Physical Design Engineer (As a consultant).

May 2015 – Dec 2016 · 1 yr 7 mos · Bangalore

Block level Physical Design from RTL to GDS on blocks at low end tech nodes.
Block Level Floorplanning.
Place and Route.
Clock Tree Synthesis.
Block level timing closure and signal integrity analysis &closure.
Formal verification.
PV closing (DRC,LVS,ERC,Antenna etc..)
IR analysis and fixture.
Electromigration analysis and fixture.
Low power blocks closure including low power checks.

Block level Physical DesignClock Tree SynthesisTiming closurePhysical Design

Qualcomm

Senior Physical Design Engineer Block level ( As a Consultant )

Mar 2011 – May 2015 · 4 yrs 2 mos · Bangalore

Worked in 14nm tech node and had extensive experience in 28nm tech node. Having complete understanding and working experience in HM (Hard macro) level implementation of the Design from Netlist to GDS. Over 4 years and 4 months of experience in Physical Design and Static timing Analysis (STA) with below work
Block level Physical Design from RTL to GDS on 9+ blocks at 28nm tech nodes.
Block Level Floorplanning.
Place and Route.
Clock Tree Synthesis.
Block level timing closure and signal integrity analysis &closure.
Formal verification.
PV closing (DRC,LVS,ERC,Antenna etc..)
IR analysis and fixture.
Electromigration analysis and fixture.
Low power blocks closure including low power checks.
Recipient of “Outstanding Performer of Quarter” award at SmartPlay.