Srijani Pal — Software Engineer

*STA and synthesis engineer *confident in converging timing and meeting TECO schedule *can do what-if analysis in PT-DMSA for clock pull/push ECO *can do detail timing analysis and correlation tasks *experience to handle and debug LEC/ERC/CTS sanity issues *Have understanding of UPF *experience in analysis and solving STA/asynchronous timing checks and several TECO tasks *have handled synthesis and Quality checks tasks *have handled and co-worked with IR team on dynamic power impact of Timing ECO *confident with timing concepts and able to work as team to solve real time issues

Stackforce AI infers this person is a VLSI design engineer with expertise in synthesis and timing analysis.

Location: Bengaluru, Karnataka, India

Experience: 5 yrs