Ernesto Conde

Co-Founder

Guadalajara, Jalisco, Mexico14 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Co-Founder and CTO with extensive semiconductor expertise.
Proficient in advanced chip design and verification engineering.
Strong background in PDK management and EDA tools.

Stackforce AI infers this person is a semiconductor design expert with a focus on ASIC and chip design solutions.

Contact

Skills

Core Skills

PdkSemiconductorsAsicDftAnalog Circuit Design

Other Skills

PDK managementEDA tools managementCAD flow automationRTL DesignVerificationSynthesisPhysical DesignuArch ExplorationNetworkingFPGA prototypingIP integrationPlace & RouteProcessorsCDCSTA

About

Steering Circuify Semiconductors as its Co-Founder and CTO, I specialize in transforming chip design complexities into competitive business advantages. Excelling in PDK management, EDA tool mastery, and CAD flow automation, I have honed my expertise in pushing the boundaries of semiconductor technology.

Experience

14 yrs 3 mos

Total Experience

7 yrs 1 mo

Average Tenure

8 yrs 1 mo

Current Experience

Tecnológico de monterrey

Adjunct Professor — ASIC Design

Sep 2025 – Dec 2025 · 3 mos · Guadalajara, Jalisco, Mexico · Hybrid

Teaching ASIC Design as part of the Engineering program at Tecnológico de Monterrey.
The course focuses on digital and mixed-signal System-on-Chip (SoC) design, including RTL development, verification, and physical implementation flows.
As part of my role, I mentor student projects, bridging academic learning with real-world semiconductor design practices through industry–academia collaboration

Fathom radiant

ASIC Digital Design Engineer

Feb 2023 – Feb 2024 · 1 yr · Boulder, Colorado, United States · Remote

RTL Design
uArch Exploration
Networking
FPGA prototyping
IP integration/evaluation (mem compilers/physical IP)

RTL DesignuArch ExplorationNetworkingFPGA prototypingIP integrationASIC

Amd

ASIC FE | DFT Engineer

Jun 2018 – Jun 2021 · 3 yrs · Remote

ASIC Front-End | DFT Design Engineer:
CDC,STA, Timing constraint development & Debug
Full chip Formal Equivalence.
IP integration (RTL/Verification) to SoC.
Interfacing with Physical Design team( supporting Floorplanning & hierarchy exploration)
DFT insertion and verification (Scan Insertion/compression/ATPG/GLS)

CDCSTADFTIP integration

Firstpass is now a part of synopsys, inc.

ASIC Design Engineer

May 2018 – Jun 2021 · 3 yrs 1 mo · Remote

RTL2GDSII implementations:
RTL Design, Lint, CDC/RDC, Synthesis, Formal equivalence/LEC, timing constraints (SDC), scan insertion, DFT, ATPG, STA, GLS, chip level Physical Design Implementation & ECO implementations.
EDA Tools management and setup

RTL DesignLintSynthesisDFTECO implementationsASIC

Circuify semiconductors

Co-Founder | CTO

Apr 2018 – Present · 8 yrs 1 mo

Unlock the full potential of your technology with our chip design and verification engineering solutions. Partner with our Nearshore team to elevate your development process and gain a competitive edge in your business. Let's collaborate to achieve success!
PDK management, enablement, and support.
Efficient EDA tools management and setup.
Advanced CAD flows setup/automation.
Comprehensive solutions in RTL Design, Verification (UVM & Formal), Synthesis, DFT, Physical Design, Timing Closure, and Physical Verification.

PDK managementEDA tools managementCAD flow automationRTL DesignVerificationSynthesis+4

Nxp semiconductors

ASIC Physical Design Engineer

May 2017 – May 2018 · 1 yr · Guadalajara Area, Mexico

ASIC Physical Design of SerDes IPs:
Back-end Floorplanning, Place & Route, ECO implementations, Timing closure (STA), and Physical verifications (DRC/LVS).
Handling designs using deep sub-micron Finfet technology.

Back-end FloorplanningPlace & RouteECO implementationsTiming closureASIC

Intel corporation

2 roles

FPGA Design | Emulation Engineer

Mar 2016 – Apr 2017 · 1 yr 1 mo

Responsible of creating SoC’s FPGA Prototype/Emulation models from RTL to Bitfile:
Design constraint, synthesis, partitioning, floor planning, place & route, and timing closure (STA).
System Integration and platform-level debug of FPGA systems.
Lab bring-up and testing of prototype/emulation models using real devices

Design constraintSynthesisTiming closureASIC

Analog Engineer

Feb 2011 – Mar 2016 · 5 yrs 1 mo

Lead Electrical validation, compliance testing, and Analog IP design verification of High-speed/Low-power PHY layers (SerDes) for several protocols:
MIPI-DPHY, USB, SDIO, RGMII & GPIOs.
Signal integrity analysis, channel characterization measurements, statistical analysis, and test automation using scripting languages (python, TCL).

Electrical validationAnalog IP design verificationSignal integrity analysisAnalog Circuit Design