Rishi Verma

DevOps Engineer

Bengaluru, Karnataka, India18 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 18 years of experience in VLSI domain.
  • Expertise in Physical Design and Verification.
  • Proven leadership in executing complex DDR designs.
Stackforce AI infers this person is a Semiconductor Design Expert with extensive experience in VLSI and Physical Design.

Contact

LinkedIn

Skills

Core Skills

Physical DesignVery-large-scale Integration (vlsi)Physical Verification

Other Skills

FloorplanningPlace & RouteLECStatic Timing AnalysisLow-power DesignFormal VerificationClock Tree SynthesisLVSCadence VirtuosoPerlMixed SignalDRCDevice ModelingCadence Virtuoso Layout EditorPerl Script

About

18+ years of experience in VLSI domain related to Physical Design, Physical Verification, Layout design, Automation, PDK etc

Experience

18 yrs 9 mos
Total Experience
3 yrs 9 mos
Average Tenure
9 yrs 9 mos
Current Experience

Qualcomm

3 roles

Engineer, Sr Staff/Manager

Jan 2024 – Present · 2 yrs 4 mos · Bengaluru, Karnataka, India

Engineer, Sr Staff

Promoted

Jan 2022 – Jan 2024 · 2 yrs · Bengaluru, Karnataka, India

  • Responsible to lead and execute Physical Design including signoff closure for DDR designs across multiple projects.
FloorplanningVery-Large-Scale Integration (VLSI)Place & RoutePhysical DesignLECStatic Timing Analysis+2

Staff Engineer

Aug 2016 – Jan 2022 · 5 yrs 5 mos · Bengaluru, Karnataka, India

  • Responsible to execute Physical Design Implementation of DDRSS Wrapper and SUBHMs including signoff closure across multiple projects from 14nm to 4nm technology.
FloorplanningPhysical DesignPhysical VerificationFormal VerificationClock Tree SynthesisPlace & Route

Intel

Technical Lead

Jan 2014 – Jan 2015 · 1 yr · Bengaluru, Karnataka, India

Lsi

Design Engineer

Jan 2011 – Jan 2014 · 3 yrs · Bengaluru Area, India

  • Worked as Design Engineer in PDK Group.

Ibm

Design Engineer

Jan 2008 – Jan 2011 · 3 yrs · Bengaluru Area, India

  • Worked as a Design Engineer in STG (System & Technology Group) group.

Ams ag

Consultant

Jan 2007 – Jan 2007 · 0 mo · Unterpremstätten, Austria

  • Worked on ESD structure.

Newlogic

Design Engineer

Jan 2007 – Jan 2007 · 0 mo · Lustenau, Austria

  • Design Engineer, Analog and Mixed signal group.

Wipro technologies

Project Engineer

Jan 2006 – Jan 2008 · 2 yrs · Bengaluru Area, India

  • Worked as Project Engineer in (AMS) Analog and Mixed Signal Group.

Defence research and development organisation

3rd Year Summer Internship

May 2005 – Jul 2005 · 2 mos · New Delhi, India

  • Study on Silicon Device Fabrication Process.

Education

Indian Institute of Technology, Roorkee

Bachelor of Technology (B.Tech.) — Electrical Engineering

Jan 2002 – Jan 2006

Manipal University

Master of Science — Microelectronics

Jan 2009 – Jan 2012

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